Setting The Rx Equalization; Agc; Dfe - Xilinx Virtex-6 FPGA User Manual

Chapter 4: Receiver
Table 4-5: RX Equalization Attributes (Cont'd)

Setting the RX Equalization

This section describes how the AGC, DFE, and CTLE are configured.

AGC

The AGC is auto-adapting.

DFE

The DFE is auto-adapting but requires some training control parameters to be set. For
modes that use the internal 8B/10B and PRBS blocks,
DFE_TRAIN_CTRL_LANE<n>[15:13] = 100. For modes that use the internal 64B/66B
blocks, DFE_TRAIN_CTRL_LANE<n>[15:13] = 001.
108
Attribute
RX_CTLE_CTRL_LANE0
RX_CTLE_CTRL_LANE1
RX_CTLE_CTRL_LANE2
RX_CTLE_CTRL_LANE3
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Type
16-bit Hex This attribute controls the RX CTLE peaking.
[15:8]: Reserved. Tie these inputs to 8'h00.
[7:4]: RX CTLE Peak Control. The peaking
is mainly focused around 2.5 GHz.
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
[3:0]: Reserved. Tie these inputs to 4'hF.
Virtex-6 FPGA GTH Transceivers User Guide
Description
dB - Nominal
0.15
0.36
0.74
0.96
1.98
2.19
2.71
2.88
4.15
4.32
4.64
4.79
5.20
5.34
5.54
5.67
UG371 (v2.0) February 16, 2010