Xilinx Virtex-6 FPGA User Manual page 49

X-Ref Target - Figure 2-4
PLL
CLKIN
PFD
PLL Block
The feedback divider value (M), part of the PLL_CFG0 attribute, is set by the
Virtex-6 FPGA GTH Transceiver Wizard. The TX output lane divider (D
TXRATE port, and the RX output lane divider (D
Equation 2-1
Equation 2-2
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
Charge Loop
Pump Filter
Feedback
Divider: M
Figure 2-4: PLL Block Diagram
shows how to determine the TX line rate (Gb/s).
f
TX_LineRate
shows how to determine the RX line rate (Gb/s).
f
RX_LineRate
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Interface
VCO
Block
) is set by the RXRATE ports.
R
M
×
f -------
=
PLLClkin
D
T
M
×
f ------- -
=
PLLClkin
D
R
PLL
Lane 0
TX Div:
TX PMA
D
T
RX Div:
RX CDR
D
R
Lane 1
TX Div:
TX PMA
D
T
RX Div:
RX CDR
D
R
Lane 2
TX Div:
TX PMA
D
T
RX Div:
RX CDR
D
R
Lane 3
TX Div:
TX PMA
D
T
RX Div:
RX CDR
D
R
UG371_c2_15_120809
) is set by the
T
Equation 2-1
Equation 2-2
49