Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

Chapter 4: Receiver
X-Ref Target - Figure 4-4
The shared Quad PLL provides a base clock to the phase interpolator. The phase
interpolator in term produces fine, evenly spaced sampling phases to allow the CDR state
machine to have fine phase control. The CDR state machine can track an incoming data
stream with a frequency offset, usually no more than ±100 PPM, from the local PLL
reference clock.

Ports and Attributes

There are no ports in the CDR block.
Table 4-6
Table 4-6: RX CDR Attributes
110
Figure 4-4: CDR Sampler Positions
defines the RX CDR attributes.
Attribute
RX_CDR_CTRL0_LANE0
RX_CDR_CTRL0_LANE1
RX_CDR_CTRL0_LANE2
RX_CDR_CTRL0_LANE3
RX_CDR_CTRL1_LANE0
RX_CDR_CTRL1_LANE1
RX_CDR_CTRL1_LANE2
RX_CDR_CTRL1_LANE3
RX_CDR_CTRL2_LANE0
RX_CDR_CTRL2_LANE1
RX_CDR_CTRL2_LANE2
RX_CDR_CTRL2_LANE3
RX_LOOP_CTRL_LANE0
RX_LOOP_CTRL_LANE1
RX_LOOP_CTRL_LANE2
RX_LOOP_CTRL_LANE3
www.xilinx.com
E E
0 1
D D
0 1
Type
16-bit Hex Reserved. Use the recommended values from the
Virtex-6 FPGA GTH Transceiver Wizard.
16-bit Hex Reserved. Use the recommended values from the
Virtex-6 FPGA GTH Transceiver Wizard.
16-bit Hex Reserved. Use the recommended values from the
Virtex-6 FPGA GTH Transceiver Wizard.
16-bit Hex Reserved. Use the recommended values from the
Virtex-6 FPGA GTH Transceiver Wizard.
Virtex-6 FPGA GTH Transceivers User Guide
E
2
UG371_c4_05_120709
Description
UG371 (v2.0) February 16, 2010