Rx Pattern Checker; Functional Description - Xilinx Virtex-6 FPGA User Manual

Chapter 4: Receiver

RX Pattern Checker

Functional Description

The GTH receiver contains a built-in pattern checker block. The checker supports the
following PRBS patterns:
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In 64B/66B mode (for example, when the GTH transceiver is configured with the
10GBASE-R protocol), the checker is forced into PRBS31 mode when PRBS31 test pattern
mode is enabled.
The PRBS checker module implements a 32-bit error counter and a 48-bit timer. The error
counter and timer function as follows:
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The error and sample counters saturate when they reach the maximum value.
In pattern check mode, data does not appear on RXDATA ports.
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PRBS7
PRBS9
PRBS11
PRBS23
PRBS31
The first read of any error counter/timer register latches both the error counter/timer
in shadow flops.
If the read was of an error counter and clear-on-read is on, both the timer and error
counter are cleared.
Reads of just the timer register (i.e., without first reading the error counter) do not
clear the error count/timer, even if clear-on-read mode is on.
Subsequent reads from error counter/timer addresses greater than the previous read
address only read the shadow flops, do not read the actual state of the error
counter/timer, and do not clear the error counter timer.
Subsequent reads from error counter/timer addresses equal to or less than the read of
the previous error counter/timer start the process over.
www.xilinx.com Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010