Xilinx Virtex-6 FPGA User Manual page 29

Table 1-5: GTH Quad Attribute Summary (Cont'd)
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
Attribute
TX_CLK_SEL1_LANE0
TX_CLK_SEL1_LANE1
TX_CLK_SEL1_LANE2
TX_CLK_SEL1_LANE3
TX_DISABLE_LANE0
TX_DISABLE_LANE1
TX_DISABLE_LANE2
TX_DISABLE_LANE3
TX_FABRIC_WIDTH0
TX_FABRIC_WIDTH1
TX_FABRIC_WIDTH2
TX_FABRIC_WIDTH3
TX_P0P0S_CTRL
TX_P1P2_CTRL
TX_PREEMPH_LANE0
TX_PREEMPH_LANE1
TX_PREEMPH_LANE2
TX_PREEMPH_LANE3
TX_PWR_RATE_OVRD_LANE0
TX_PWR_RATE_OVRD_LANE1
TX_PWR_RATE_OVRD_LANE2
TX_PWR_RATE_OVRD_LANE3
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Port and Attribute Summary
Type
16-bit Hex
16-bit Hex
Integer
16-bit Hex
16-bit Hex
16-bit Hex
16-bit Hex
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