Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

Ports and Attributes

Table 4-9
.
Table 4-9: RX Pattern Checker Ports
Port Dir
RXCODEERR0[7:0] Out
RXCODEERR1[7:0]
RXCODEERR2[7:0]
RXCODEERR3[7:0]
Table 4-10
Table 4-10: RX Pattern Checker Attributes
Attribute
PCS_MISC_CFG_0_LANE0
PCS_MISC_CFG_0_LANE1
PCS_MISC_CFG_0_LANE2
PCS_MISC_CFG_0_LANE3
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
defines the RX pattern checker ports.
Clock Domain
RXUSERCLKIN0 These outputs indicate an error occurred on RXDATA<n> or they
are used as an extension of RXDATA<n> depending on the mode
RXUSERCLKIN1
selected in the receive datapath:
RXUSERCLKIN2
8B/10B: These outputs indicate that RXDATA<n> is the result of
RXUSERCLKIN3
an 8B/10B code error.
RXCODEERR<n>[7] corresponds to RXDATA<n>[63:56]
RXCODEERR<n>[6] corresponds to RXDATA<n>[55:48]
RXCODEERR<n>[5] corresponds to RXDATA<n>[47:40]
RXCODEERR<n>[4] corresponds to RXDATA<n>[39:32]
RXCODEERR<n>[3] corresponds to RXDATA<n>[31:24]
RXCODEERR<n>[2] corresponds to RXDATA<n>[23:16]
RXCODEERR<n>[1] corresponds to RXDATA<n>[15:8]
RXCODEERR<n>[0] corresponds to RXDATA<n>[7:0]
64B/66B: RXCODEERR<n>[0] indicates a 64B/66B code error.
RXCODEERR<n>[7:1] are not used for this mode.
Raw mode: These outputs are used as part of RXDATA<n>[79:72].
defines the RX pattern checker attributes.
Type
16-bit Hex This attribute sets the polarity and PRBS configuration.
[15:12]: Reserved. Use the recommended values from the Virtex-6
FPGA GTH Transceiver Wizard.
[11]: Invert TX polarity
[10]: RX polarity override enable
[9]: RX polarity override value
[8]: Reset the PRBS error counter when read
[7]: Revert bit order of parallel data to serializer/deserializer TX
[6]: Revert bit order of parallel data from serializer/deserializer RX
[5:0]: Reserved. Use the recommended values from the Virtex-6 FPGA
GTH Transceiver Wizard.
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RX Pattern Checker
Description
Description
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