Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

Chapter 4: Receiver
Figure 4-2
X-Ref Target - Figure 4-2

Ports and Attributes

Table 4-4
Table 4-4: RX Equalization Ports
106
provides a top-level illustration of the AFE with the CTLE, DFE, and CDR.
RX AFE
Figure 4-2: RX Equalization Block Diagram
defines the RX equalization ports.
Port
DFETRAINCTRL0
DFETRAINCTRL1
DFETRAINCTRL2
DFETRAINCTRL3
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CTLE
Dir Clock Domain
In DCLK
Virtex-6 FPGA GTH Transceivers User Guide
DFE Adaption
Logic
DFE SIPO
CDR
UG371_c4_03_120809
Description
When the DFE is enabled,
asserting this pin overrides
completion of the DFE training.
UG371 (v2.0) February 16, 2010