Tx 64B/66B Block; Functional Description; Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

Chapter 3: Transmitter

TX 64B/66B Block

Functional Description

Some high-speed data rate protocols use 64B/66B encoding to reduce the overhead of
8B/10B encoding while retaining the benefits of an encoding scheme. The GTH transceiver
implements the 64B/66B block based on the IEEE 802.3-2008 Clause 49, "Physical Sublayer
(PCS) for 64B/66B, type 10GBASE-R." The transmit 64B/66B block includes the scrambler
and the gearbox.

Ports and Attributes

Table 3-7
Table 3-7: TX 64B/66B Block Ports
Port Dir
TXCTRL0[7:0] In
TXCTRL1[7:0]
TXCTRL2[7:0]
TXCTRL3[7:0]
TXDATA0[63:0] In
TXDATA1[63:0]
TXDATA2[63:0]
TXDATA3[63:0]
86
defines the TX 64B/66B block ports.
Clock Domain
TXUSERCLKIN0 These inputs indicate control of TXDATA<n> or they are used as
an extension of TXDATA<n> depending on the mode selected in
TXUSERCLKIN1
the transmitter datapath:
TXUSERCLKIN2
8B/10B: These inputs are asserted when TXDATA<n> is an
TXUSERCLKIN3
8B/10B K character.
TXCTRL<n>[7] corresponds to TXDATA<n>[63:56]
TXCTRL<n>[6] corresponds to TXDATA<n>[55:48]
TXCTRL<n>[5] corresponds to TXDATA<n>[47:40]
TXCTRL<n>[4] corresponds to TXDATA<n>[39:32]
TXCTRL<n>[3] corresponds to TXDATA<n>[31:24]
TXCTRL<n>[2] corresponds to TXDATA<n>[23:16]
TXCTRL<n>[1] corresponds to TXDATA<n>[15:8]
TXCTRL<n>[0] corresponds to TXDATA<n>[7:0]
64B/66B: These inputs are 64B/66B control bits.
Raw mode: These inputs are used as part of TXDATA<n>[71:64].
TXUSERCLKIN0 This input bus is the transmit data bus of the transmit interface
from the FPGA.
TXUSERCLKIN1
TXUSERCLKIN2
TXUSERCLKIN3
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Description
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010