Pbist Control Registers - Texas Instruments TMS570LC4357 Technical Reference Manual

PBIST Control Registers

9.5 PBIST Control Registers
PBIST controller uses configuration registers for programming the algorithm and its execution. All the
configuration registers are memory mapped for access by the CPU through the Peripheral Bus interface.
The base address for the control registers is FFFF E400h.
NOTE: There is no watchdog functionality implemented in the PBIST controller. If a bad code is
executed, the PBIST runs forever. The PBIST controller does not guard against this
situation.
Registers are accessible only when the clock to the PBIST controller is active. The clock is
activated by first writing 1h to the PACT register.
Offset Acronym
160h RAMT
164h DLR
180h PACT
184h PBISTID
188h OVER
190h FSRF0
198h FSRC0
19Ch FSRC1
1A0h FSRA0
1A4h FSRA1
1A8h FSRDL0
1B0h FSRDL1
1C0h ROM
1C4h ALGO
1C8h RINFOL
1CCh RINFOU
412
Programmable Built-In Self-Test (PBIST) Module
Table 9-1. PBIST Registers
Register Description
RAM Configuration Register
Datalogger Register
PBIST Activate/Clock Enable Register
PBIST ID Register
Override Register
Fail Status Fail Register 0
Fail Status Count Register 0
Fail Status Count Register 1
Fail Status Address Register 0
Fail Status Address Register 1
Fail Status Data Register 0
Fail Status Data Register 1
ROM Mask Register
ROM Algorithm Mask Register
RAM Info Mask Lower Register
RAM Info Mask Upper Register
Copyright © 2018, Texas Instruments Incorporated
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Section
Section 9.5.1
Section 9.5.2
Section 9.5.3
Section 9.5.4
Section 9.5.5
Section 9.5.6
Section 9.5.7
Section 9.5.7
Section 9.5.8
Section 9.5.8
Section 9.5.9
Section 9.5.9
Section 9.5.10
Section 9.5.11
Section 9.5.12
Section 9.5.13
SPNU563A – March 2018
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