Texas Instruments TMS570LC4357 Technical Reference Manual page 913

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22.3.23 ADC Results Memory Configuration Register (ADBNDCR)
ADC Results Memory Configuration Register (ADBNDCR) [offset = 0x58] is shown in
described in Table
Refer to Section 22.2.7
RAM.
Figure 22-45. ADC Results Memory Configuration Register (ADBNDCR) [offset = 58h]
31
Reserved
R-0
15
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-29. ADC Results Memory Configuration Register (ADBNDCR) Field Descriptions
Bit Field
31-25 Reserved
24-16 BNDA
15-9 Reserved
8-0 BNDB
SPNU563A – March 2018
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22-29.
for further details on how the conversion results are stored in the ADC results'
25
9
Value Description
0 Reads return 0. Writes have no effect.
Buffer Boundary A. These bits determine the memory available for the Event Group conversion
results. The memory available is specified in terms of pairs of result buffers.
Any operation mode read/write:
0 Event Group conversions are not required. If Event Group conversions are performed with the
BNDA value of 0, then the Event Group memory size will default to 1024 words. For proper
usage of the ADC results memory, configure the BNDA value to be non-zero and lower than the
BNDB value.
0-1FFh A total of (2 × BNDA) buffers are available in the ADC results memory for storing Event Group
conversion results.
0 Reads return 0. Writes have no effect.
Buffer Boundary B. These bits specify the number of buffers allocated for the Event Group plus
the number of buffers allocated for the Group1. The number of buffer pairs allocated for storing
Group1 conversion results can be determined by subtracting BNDA from BNDB. As a result,
BNDB must always be specified as greater than or equal to BNDA.
Any operation mode read/write:
0 Event Group as well as Group1 conversions are not required.
0-1FFh A total of 2 × (BNDB - BNDA) buffers are available in the ADC results memory for storing
Group1 conversion results.
Copyright © 2018, Texas Instruments Incorporated
24
8
Analog To Digital Converter (ADC) Module
ADC Registers
Figure 22-45
BNDA
R/W-0
BNDB
R/W-0
and
16
0
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