Texas Instruments TMS570LC4357 Technical Reference Manual page 114

Introduction
32 kB Icache
& Dcache w /
ECC
Dual Cortex -R5F
CPUs in lockstep
Acp_m Axi-m
Dma
portA
CPU Interconnect Subsystem
Flash Flash
Acp_s sram portB portA emif
512kB POM
SRAM
4MB Flash
w/
&
ECC
128kB
EMIF
Flash for
EEPROM
Emulation
w/ ECC
114
Architecture
Figure 2-1. Architectural Block Diagram
NMPU
Ps_scr_m pom
Axi-pp Dma portB
Ps_scr_s pcr1
PCR1
ESM IOMM
Lockstep
PMM
VIMs
RTI EPC
DCC1 SCM
STC1 SYS
CCM-
DCC2
R5F
STC2
Copyright © 2018, Texas Instruments Incorporated
NMPU
Dma_portA
DMM
DMA DAP
dap dmm
Peripheral Interconnect Subsystem
pcr2 Sdc mmr port
PCR2 SDC MMR
EMIF
SCI3
Slave
SCI4
EMAC
Slaves
I2C1
eQEP
1,2
I2C2
eCAP
FlexRay
1..6
ePWM
GIO
1..7
N2HET1
N2HET2
MibADC 1
MibADC 2
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EMAC
HTU1 FTU HTU2
NMPU
htu1 ftu htu2
pcr3 crc1
PCR3 CRC1
DCAN1
DCAN2
DCAN3
DCAN4
MibSPI1
MibSPI2
MibSPI3
MibSPI4
MibSPI5
LIN1/SCI1
LIN2/SCI2
SPNU563A – March 2018
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emac
crc2
CRC2