Texas Instruments TMS570LC4357 Technical Reference Manual page 225

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2.5.3.5 Peripheral Protection Set Register 0 (PPROTSET0)
There is one bit for each quadrant for PS0 to PS7.
The following are the ways that quadrants are used within a PS frame:
a. The slave uses all the four quadrants.
Only the bit corresponding to the quadrant 0 of PSn is implemented. It protects the whole 1K-byte
frame. The remaining three bits are not implemented.
b. The slave uses two quadrants.
Each quadrant has to be in one of these groups: (Quad 0 and Quad 1) or (Quad 2 and Quad 3).
For the group Quad0/Quad1, the bit quadrant 0 protects both quadrants 0 and 1. The bit quadrant 1 is
not implemented.
For the group Quad2/Quad3, the bit quadrant 2 protects both quadrants 2 and 3. The bit quadrant 3 is
not implemented
c. The slave uses only one quadrant.
In this case, the bit, as specified in
The above arrangement is true for all the peripheral selects (PS0 to PS31), presented in
Section 2.5.3.12. This register holds bits for PS0 to PS7 and is shown in
Table 2-90.
NOTE: Writes to unimplemented bits have no effect and reads are 0.
Figure 2-76. Peripheral Protection Set Register 0 (PPROTSET0) (offset = 20h)
31
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-90. Peripheral Protection Set Register 0 (PPROTSET0) Field Descriptions
Bit Field
31-0 PS[7-0]QUAD[3-0]
PROTSET
SPNU563A – March 2018
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Table 2-90, protects the slave.
PS[7-0]QUAD[3-0]PROTSET
R/WP-0
Value Description
Peripheral select quadrant protection set.
0 Read: The peripheral select quadrant an be written to and read from in both user and
privileged modes.
Write: The bit is unchanged.
1 Read: The peripheral select quadrant can be written to only in privileged mode, but it can be
read in both user and privileged modes.
Write: The corresponding bit in PPROTSET0 and PPROTCLR0 registers is set to 1.
Copyright © 2018, Texas Instruments Incorporated
System and Peripheral Control Registers
Section 2.5.3.6
Figure 2-76 and described in
Architecture
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