Texas Instruments TMS570LC4357 Technical Reference Manual page 224

System and Peripheral Control Registers
2.5.3.3 Peripheral Memory Protection Clear Register 0 (PMPROTCLR0)
This register is shown in
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to unimplemented bits have no effect and reads are 0.
Figure 2-74. Peripheral Memory Protection Clear Register 0 (PMPROTCLR0) (offset = 10h)
31
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-88. Peripheral Memory Protection Clear Register 0 (PMPROTCLR0) Field Descriptions
Bit Field
31-0 PCS[31-0]PROTCLR
2.5.3.4 Peripheral Memory Protection Clear Register 1 (PMPROTCLR1)
This register is shown in
NOTE: Only those bits that have a slave at the corresponding bit position are implemented. Writes
to unimplemented bits have no effect and reads are 0.
Figure 2-75. Peripheral Memory Protection Clear Register 1 (PMPROTCLR1) (offset = 14h)
31
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-89. Peripheral Memory Protection Clear Register 1 (PMPROTCLR1) Field Descriptions
Bit Field
31-0 PCS[63-32]PROTCLR
224
Architecture
Figure 2-74 and described in
PCS[31-0]PROTCLR
R/WP-0
Value Description
Peripheral memory frame protection clear.
0 Read: The peripheral memory framen can be written to and read from in both user and
privileged modes.
Write: The bit is unchanged.
1 Read: The peripheral memory framen can be written to only in privileged mode, but it can be
read in both user and privileged modes.
Write: The corresponding bit in PMPROTSET0 and PMPROTCLR0 registers is cleared to 0.
Figure 2-75 and described in
PCS[63-32]PROTCLR
R/WP-0
Value Description
Peripheral memory frame protection clear.
0 Read: The peripheral memory framen can be written to and read from in both user and
privileged modes.
Write: The bit is unchanged.
1 Read: The peripheral memory framen can be written to only in privileged mode, but it can be
read in both user and privileged modes.
Write: The corresponding bit in PMPROTSET1 and PMPROTCLR1 registers is cleared to 0.
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Table 2-88.
Table 2-89.
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SPNU563A – March 2018
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