Texas Instruments TMS570LC4357 Technical Reference Manual page 133

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Address
Register Name
Offset
8h UERRSTAT
10h FIFOFULLSTAT
14h OVRFLWSTAT
20h UERRADDR0
24h UERRADDR1
SPNU563A – March 2018
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Table 2-4. EPC Registers Bit Mapping
Bit # Error Source
Uncorrectable ECC for
0
DMA interface
Uncorrectable ECC for
1
PS_SCR_M interface
0 CPU Correctable ECC error
1 Reserved
Correctable ECC for
2
DMA interface
Correctable ECC for
3
PS_SCR_M interface
Correctable ECC error from L2
4
SRAM
0 CPU Correctable ECC error
1 Reserved
Correctable ECC for
2
DMA interface
Correctable ECC for
3
PS_SCR_M interface
Correctable ECC error from L2
4
SRAM
Uncorrectable ECC for
31:0
DMA interface
Uncorrectable ECC for
31:0
PS_SCR_M interface
Copyright © 2018, Texas Instruments Incorporated
Memory Organization
Remark
• Bit associates with the Uncorrectable ECC error
detected by the CPU Interconnect Subsystem
for the DMA interface
• See Interconnect chapter for details on the
ECC generation and evaluation for DMA
interface
• Bit associates with the Uncorrectable ECC error
detected by the CPU Interconnect Subsystem
for the PS_SCR_M interface
• See Interconnect chapter for details on the
ECC generation and evaluation for DMA
interface
• Bit associates with the FIFO full status for the
interface that is used to capture the CPU
correctable error event
• Correctable error event exported by CPU's
event bus.
• Bit associates with the FIFO full status for the
interface that is used to capture the DMA
correctable error event
• Correctable error event detected by the CPU
Interconnect Subsystem for the DMA PortA
interface.
• Bit associates with the FIFO full status for the
interface that is used to capture the
PS_SCR_M correctable error event
• Correctable error event detected by the CPU
Interconnect Subsystem for the PS_SCR_M
interface.
• Bit associates with the FIFO full status for the
interface that is used to capture the L2 SRAM
correctable error event
• Correctable error event detected by the L2
SRAM wrapper during the read phase of a
Read-Modify-Write operation due to a less than
64-bit write from the bus master.
• Bit associates with the FIFO overflow status for
the interface that is used to capture the CPU
correctable error event
• Bit associates with the FIFO overflow status for
the interface that is used to capture the DMA
correctable error event
• Bit associates with the FIFO overflow status for
the interface that is used to capture the
PS_SCR_M correctable error event
• Bit associates with the FIFO overflow status for
the interface that is used to capture the L2
SRAM correctable error event
• Uncorrectable error address register for the
DMA interface
• Uncorrectable error address register for the
PS_SCR_M interface
Architecture
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