Texas Instruments TMS570LC4357 Technical Reference Manual page 183

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2.5.1.31 Clock Test Register (CLKTEST)
The CLKTEST register, shown in
supplied to the ECLK pin for test and debug purposes.
NOTE: Clock Test Register Usage
This register should only be used for test and debug purposes.
31
23
Reserved
15 12
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Bit Field
31-27 Reserved
26 TEST
25 RANGEDETCTRL
24 RANGEDETENASSEL
23-20 Reserved
19-16 CLK_TEST_EN
15-12 Reserved
SPNU563A – March 2018
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Figure 2-38
Figure 2-38. Clock Test Register (CLKTEST) (offset = 8Ch)
Reserved
R-0
20
R-0
11
SEL_GIO_PIN
R/WP-0
Table 2-50. Clock Test Register (CLKTEST) Field Descriptions
Value Description
0 Reads return 0. Writes have no effect.
0 This bit is used for test purposes. It must be written to 0.
Range detection control. This bit's functionality is dependant on the state of the
RANGEDETENSSEL bit (Bit 24) of the CLKTEST register.
0 The clock monitor range detection circuitry (RANGEDETECTENABLE) is disabled.
1 The clock monitor range detection circuitry (RANGEDETECTENABLE) is enabled.
Selects range detection enable. This bit resets asynchronously on power on reset.
0 The range detect enable is generated by the hardware in the clock monitor wrapper.
1 The range detect enable is controlled by the RANGEDETCTRL bit (Bit 25) of the
CLKTEST register.
0 Reads return 0. Writes have no effect.
Clock test enable. This bit enables the clock going to the ECLK pin. This bit field enables
or disables clock going to device pins. Two pins in a device can get clock sources by
enabling CLK_TEST_EN bits. One pin is the ECP and second pin is a device specific GIO
pin. These bits need to asynchronously reset.
Note: The ECLK pin must also be placed into Functional mode by setting the
ECPCLKFUN bit to 1 in the SYSPC1 register.
5h Clock going to ECLK pin is enabled.
Others Clock going to ECLK pin is disabled.
0 Reads return 0. Writes have no effect.
Copyright © 2018, Texas Instruments Incorporated
System and Peripheral Control Registers
and described in Table 2-50, controls the clock signal that is
27 26
TEST
R/WP-0
19
8 7 5
Reserved
R-0
25
RANGEDET RANGEDET
CTRL ENASSEL
R/WP-0 R/WP-0
CLK_TEST_EN
R/WP-Ah
4
SEL_ECP_PIN
R/WP-0
Architecture
24
16
0
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