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27-30. ECC Control and Status Register (DCAN ECC CS) [offset = 2Ch]
27-31. ECC Single-Bit Error Code Register (DCAN ECC SERR) [offset = 30h]
27-58. IF2 Command Registers (DCAN IF2CMD) [offset = 120h]
27-60. IF2 Mask Register (DCAN IF2MSK) [offset = 124h]
27-62. IF2 Arbitration Register (DCAN IF2ARB) [offset = 128h]
27-64. IF2 Message Control Register (DCAN IF2MCTL) [offset = 12Ch]
27-67. IF2 Data A Register (DCAN IF2DATA) [offset = 130h]
27-68. IF2 Data B Register (DCAN IF2DATB) [offset = 134h]
SPNU563A - March 2018
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59
List of Figures
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