Texas Instruments TMS570LC4357 Technical Reference Manual page 984

N2HET Functional Description
23.2.5.14 I/O Pull Control Feature
Figure 23-24. I/O Block Diagram Including Pull Control Logic
Output enable
Input enable
Pull control disable
Pull select
The following apply if the device is under reset:
• Pull control: The reset pull control on the pins is enabled and a pulldown is configured.
• Input buffer: The input buffer is enabled.
• Output buffer: The output buffer is disabled.
The following apply if the device is out of reset:
• Pull control: The pull control is enabled by clearing the corresponding bit in the N2HET Pull Disable
Register (HETPULDIS). In this case, if the corresponding bit in the N2HET Pull Select Register
(HETPSL) is set, the pin will have a pull-up; if the bit in the N2HET Pull Select Register (HETPSL) is
cleared, the pin will have a pull-down. If the bit in the N2HET Pull Disable Register (HETPULDIS) is
set, there is no pull-up or pull-down on the pin.
• Input buffer: The input buffer is disabled only if the pin direction is set to input AND the pull control is
disabled AND pull down is selected as the pull bias. In all other cases, the input buffer is enabled.
NOTE: The pull-disable logic depends on the pin direction. If the pin is configured as output, then
the pulls are disabled automatically. If the pin is configured as input, the pulls are enabled or
disabled depending on the pull disable register bit.
• Output buffer: A pin can be driven as an output pin if the corresponding bit in the N2HET Direction
Register (HETDIR) is set AND the open-drain feature (N2HET Open Drain Register (HETPDR)) is not
enabled. See Section 23.2.5.15
The behavior of the input buffer, output buffer, and the pull control is summarized in
input buffer is disabled, it appears as a logic low to on-chip logic.
984
High-End Timer (N2HET) Module
Data out
Data in
for more details.
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N2HET pin
Pull control
logic
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Table 23-9. When an
SPNU563A – March 2018