Texas Instruments TMS570LC4357 Technical Reference Manual page 30

34.3.23 eQEP Capture Period Register (QCPRD)
34.3.24 eQEP Capture Period Latch Register (QCPRDLAT)
35 Enhanced Pulse Width Modulator (ePWM) Module
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35.1 Introduction
35.1.1 Submodule Overview
35.1.2 Register Mapping
35.2 ePWM Submodules
35.2.1 Overview
35.2.2 Time-Base (TB) Submodule
35.2.3 Counter-Compare (CC) Submodule
35.2.4 Action-Qualifier (AQ) Submodule
35.2.5 Dead-Band Generator (DB) Submodule
35.2.6 PWM-Chopper (PC) Submodule
35.2.7 Trip-Zone (TZ) Submodule
35.2.8 Event-Trigger (ET) Submodule
35.2.9 Digital Compare (DC) Submodule
35.2.10 Proper Interrupt Initialization Procedure
35.3 Application Examples
35.3.1 Overview of Multiple Modules
35.3.2 Key Configuration Capabilities
35.3.3 Controlling Multiple Buck Converters With Independent Frequencies
35.3.4 Controlling Multiple Buck Converters With Same Frequencies
35.3.5 Controlling Multiple Half H-Bridge (HHB) Converters
35.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
35.3.7 Practical Applications Using Phase Control Between PWM Modules
35.4 ePWM Registers
35.4.1 Time-Base Submodule Registers
35.4.2 Counter-Compare Submodule Registers
35.4.3 Action-Qualifier Submodule Registers
35.4.4 Dead-Band Submodule Registers
35.4.5 Trip-Zone Submodule Registers
35.4.6 Event-Trigger Submodule Registers
35.4.7 PWM-Chopper Submodule Register
35.4.8 Digital Compare Submodule Registers
36 Data Modification Module (DMM)
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36.1 Overview
36.1.1 Features
36.1.2 Block Diagram
36.2 Module Operation
36.2.1 Data Format
36.2.2 Data Port
36.2.3 Error Handling
36.2.4 Interrupts
36.3 Control Registers
36.3.1 DMM Global Control Register (DMMGLBCTRL)
36.3.2 DMM Interrupt Set Register (DMMINTSET)
36.3.3 DMM Interrupt Clear Register (DMMINTCLR)
36.3.4 DMM Interrupt Level Register (DMMINTLVL)
36.3.5 DMM Interrupt Flag Register (DMMINTFLG)
36.3.6 DMM Interrupt Offset 1 Register (DMMOFF1)
36.3.7 DMM Interrupt Offset 2 Register (DMMOFF2)
36.3.8 DMM Direct Data Mode Destination Register (DMMDDMDEST)
36.3.9 DMM Direct Data Mode Blocksize Register (DMMDDMBL)
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Copyright © 2018, Texas Instruments Incorporated
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SPNU563A – March 2018
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