Texas Instruments TMS570LC4357 Technical Reference Manual page 18

23.6.2 Abbreviations, Encoding Formats and Bits
23.6.3 Instruction Description
24 High-End Timer Transfer Unit (HTU) Module
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24.1 Overview
24.1.1 Features
24.2 Module Operation
24.2.1 Data Transfers between Main RAM and N2HET RAM
24.2.2 Arbitration of HTU Elements and Frames
24.2.3 Conditions for Frame Transfer Interruption
24.2.4 HTU Overload and Request Lost Detection
24.2.5 Memory Protection
24.2.6 Control Packet RAM Parity Checking
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24.3 Use Cases
24.3.1 Example: Single Element Transfer with One Trigger Request
24.3.2 Example: Multiple Element Transfer with One Trigger Request
24.3.3 Example: 64-Bit-Transfer of Control Field and Data Fields
24.4 HTU Control Registers
24.4.1 Global Control Register (HTU GC)
24.4.2 Control Packet Enable Register (HTU CPENA)
24.4.3 Control Packet (CP) Busy Register 0 (HTU BUSY0)
24.4.4 Control Packet (CP) Busy Register 1 (HTU BUSY1)
24.4.5 Control Packet (CP) Busy Register 2 (HTU BUSY2)
24.4.6 Control Packet (CP) Busy Register 3 (HTU BUSY3)
24.4.7 Active Control Packet and Error Register (HTU ACPE)
24.4.8 Request Lost and Bus Error Control Register (HTU RLBECTRL)
24.4.9 Buffer Full Interrupt Enable Set Register (HTU BFINTS)
24.4.10 Buffer Full Interrupt Enable Clear Register (HTU BFINTC)
24.4.11 Interrupt Mapping Register (HTU INTMAP)
24.4.12 Interrupt Offset Register 0 (HTU INTOFF0)
24.4.13 Interrupt Offset Register 1 (HTU INTOFF1)
24.4.14 Buffer Initialization Mode Register (HTU BIM)
24.4.15 Request Lost Flag Register (HTU RLOSTFL)
24.4.16 Buffer Full Interrupt Flag Register (HTU BFINTFL)
24.4.17 BER Interrupt Flag Register (HTU BERINTFL)
24.4.18 Memory Protection 1 Start Address Register (HTU MP1S)
24.4.19 Memory Protection 1 End Address Register (HTU MP1E)
24.4.20 Debug Control Register (HTU DCTRL)
24.4.21 Watch Point Register (HTU WPR)
24.4.22 Watch Mask Register (HTU WMR)
24.4.23 Module Identification Register (HTU ID)
24.4.24 Parity Control Register (HTU PCR)
24.4.25 Parity Address Register (HTU PAR)
24.4.26 Memory Protection Control and Status Register (HTU MPCS)
24.4.27 Memory Protection Start Address Register 0 (HTU MP0S)
24.4.28 Memory Protection End Address Register (HTU MP0E)
24.5 Double Control Packet Configuration Memory
24.5.1 Initial Full Address A Register (HTU IFADDRA)
24.5.2 Initial Full Address B Register (HTU IFADDRB)
24.5.3 Initial N2HET Address and Control Register (HTU IHADDRCT)
24.5.4 Initial Transfer Count Register (HTU ITCOUNT)
24.5.5 Current Full Address A Register (HTU CFADDRA)
24.5.6 Current Full Address B Register (HTU CFADDRB)
24.5.7 Current Frame Count Register (HTU CFCOUNT)
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Copyright © 2018, Texas Instruments Incorporated
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SPNU563A - March 2018
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