Asynchronous N Configuration Registers (Ce2Cfg-Ce5Cfg) - Texas Instruments TMS570LC4357 Technical Reference Manual

EMIF Registers

21.3.5 Asynchronous n Configuration Registers (CE2CFG-CE5CFG)

The asynchronous n configuration registers (CE2CFG, CE3CFG, CE4CFG, and CE5CFG) are used to
configure the shaping of the address and control signals during an access to asynchronous memory
connected to CS2, CS3, CS4, and CS5, respectively. CS5 is not available on this device. It is also used to
program the width of asynchronous interface and to select from various modes of operation. This register
can be written prior to any transfer, and any asynchronous transfer following the write will use the new
configuration. The CEnCFG is shown in
Figure 21-19. Asynchronous n Configuration Register (CEnCFG) [offset = 10h - 1Ch]
31 30
(A)
SS EW
R/W-0 R/W-0
23
W_STROBE
R/W-3Fh
15 13 12
R_SETUP
R/W-Fh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
A. The EW bit must be cleared to 0.
B. This bit field must be cleared to 0 if the EMIF on your device does not have an EMIF_nWAIT pin.
Table 21-29. Asynchronous n Configuration Register (CEnCFG) Field Descriptions
Bit Field Value
31 SS
0
1
30 EW
0
1
29-26 W_SETUP 0-Fh
25-20 W_STROBE 0-3Fh
19-17 W_HOLD 0-7h
16-13 R_SETUP 0-Fh
12-7 R_STROBE 0-3Fh
6-4 R_HOLD 0-7h
3-2 TA 0-3h
1-0 ASIZE
0
1h
2h-3h
832
External Memory Interface (EMIF)
Figure 21-19
29
W_SETUP
R/W-Fh
20
(B)
(B)
R_STROBE
R/W-3Fh
Description
Select Strobe bit. This bit defines whether the asynchronous interface operates in Normal Mode or
Select Strobe Mode. See Section 21.2.6
Normal Mode enabled.
Select Strobe Mode enabled.
Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See
extended wait cycles for details. This bit field must be set to 0, if the EMIF on your device does not have
an EMIF_nWAIT pin.
Extended wait cycles disabled.
Extended wait cycles enabled.
Write setup width in EMIF_CLK cycles, minus one cycle. See
Write strobe width in EMIF_CLK cycles, minus one cycle. See
Write hold width in EMIF_CLK cycles, minus one cycle. See
Read setup width in EMIF_CLK cycles, minus one cycle. See
Read strobe width in EMIF_CLK cycles, minus one cycle. See
Read hold width in EMIF_CLK cycles, minus one cycle. See
Minimum Turn-Around time. This field defines the minimum number of EMIF_CLK cycles between reads
and writes, minus one cycle. See
Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus.
8-bit data bus
16-bit data bus
Reserved
Copyright © 2018, Texas Instruments Incorporated
and described in Table
26
19
W_HOLD
R/W-7h
7 6 4
R_HOLD
R/W-7h
for details on the two modes of operation.
Section 21.2.6.3
Section 21.2.6.3
Section 21.2.6.3
Section 21.2.6.3
Section 21.2.6.3
Section 21.2.6.3
Section 21.2.6.3 for details.
www.ti.com
21-29.
25 24
(B)
W_STROBE
R/W-3Fh
17 16
R_SETUP
R/W-Fh
3 2 1
TA ASIZE
R/W-3h R/W-0
Section 21.2.6.6
for details.
for details.
for details.
for details.
for details.
for details.
SPNU563A – March 2018
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