Dcc Counter0 Clock Source Selection Register (Dcccnt0Clksrc) - Texas Instruments TMS570LC4357 Technical Reference Manual

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15.4.11 DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC)

Figure 15-15 and Table 15-10
Figure 15-17. DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC) [offset = 28h]
31
15
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 15-12. DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC)
Bit Field
31-4 Reserved
3-0 CNT0 CLKSRC
SPNU563A – March 2018
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describe the DCC Counter0 Clock Source Selection register.
Reserved
Reserved
R-0
Field Descriptions
Value Description
0 Reads return 0. Writes have no effect.
Clock source for counter0 .
Reads in any operating mode return the current value of CLKSRC.
Writes in privileged mode select the clock source for counter0.
Refer to the device datasheet for available clock source options for counter0.
Copyright © 2018, Texas Instruments Incorporated
R-0
Dual-Clock Comparator (DCC) Module
DCC Control Registers
4 3
CNT0 CLKSRC
R/WP-5h
16
0
557