Texas Instruments TMS570LC4357 Technical Reference Manual page 754

Control Registers and Control Packets
20.3.1.45 HBCA Interrupt Channel Offset Register (HBCAOFFSET)
Figure 20-62. HBCA Interrupt Channel Offset Register (HBCAOFFSET) [offset = 154h]
31
15
Reserved
LEGEND: R = Read only; -n = value after reset
Table 20-52. HBCA Interrupt Channel Offset Register (HBCAOFFSET) Field Descriptions
Bit Field Value
31-16 Reserved 0
7-6 sbz 0
5-0 HBCA
0
1h
:
20h
21h-
3Fh
754
Direct Memory Access Controller (DMA) Module
R-0
Description
Reads return 0. Writes have no effect.
These bits should always be programmed as zero.
Channel causing HBC interrupt Group A. These bits contain the channel number of the pending
interrupt for Group A if the corresponding interrupt enable is set.
Note: Reading this location clears the corresponding interrupt pending flag (see
Section 20.3.1.40) with the highest priority.
No interrupt is pending.
Channel 0 is causing the pending interrupt Group A.
:
Channel 31 is causing the pending interrupt Group A.
Reserved
Copyright © 2018, Texas Instruments Incorporated
Reserved
R-0
8 7 6 5
sbz sbz
R-0 R-0
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16
0
HBCA
R-0
SPNU563A – March 2018
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