Ram Info Mask Upper Register (Rinfou) - Texas Instruments TMS570LC4357 Technical Reference Manual

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9.5.13 RAM Info Mask Upper Register (RINFOU)

This register is used to select the RAM groups 33 to 64 to run the algorithms selected in the ALGO
register. For an algorithm to be executed on a particular RAM group, the corresponding bit in this register
should be set to 1. The default value of this register is all 1s, which means all the RAM Info Groups would
be selected. Figure 9-18
Figure 9-18. RAM Info Mask Upper Register (RINFOU) [offset = 01CCh]
31
RINFOU3
R/W-FFh
15
RINFOU1
R/W-FFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-17. RAM Info Mask Upper Register (RINFOU) Field Descriptions
Bit Field Value
31 0
1
30 0
1
:
0 0
1
31-0 0
SPNU563A – March 2018
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and Table 9-17 illustrate this register.
24
8
Description
RAM Group 64 is not selected.
Selects group 64 for PBIST run.
RAM Group 63 is not selected.
Selects RAM group 63 for PBIST run.
:
RAM Group 33 is not selected.
Selects RAM Group 33 for PBIST run.
None of RAM Groups 33 to 64 are selected.
Copyright © 2018, Texas Instruments Incorporated
23
RINFOU2
R/W-FFh
7
RINFOU0
R/W-FFh
Programmable Built-In Self-Test (PBIST) Module
PBIST Control Registers
16
0
425