Texas Instruments TMS570LC4357 Technical Reference Manual page 13

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19.5 Interrupt Vector Table (VIM RAM)
19.5.1 Interrupt Vector Table Operation
19.5.2 VIM ECC Syndrome
19.5.3 Interrupt Vector Table Initialization
19.5.4 Interrupt Vector Table ECC Testing
19.6 VIM Wakeup Interrupt
19.7 Capture Event Sources
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19.8 Examples
19.8.1 Examples - Configure CPU To Receive Interrupts
19.8.2 Examples - Register Vector Interrupt and Index Interrupt Handling
19.9 VIM Control Registers
19.9.1 Interrupt Vector Table ECC Status Register (ECCSTAT)
19.9.2 Interrupt Vector Table ECC Control Register (ECCCTL)
19.9.3 Uncorrectable Error Address Register (UERRADDR)
19.9.4 Fallback Vector Address Register (FBVECADDR)
19.9.5 Single-Bit Error Address Register (SBERRADDR)
19.9.6 VIM Offset Vector Registers
19.9.7 IRQ Index Offset Vector Register (IRQINDEX)
19.9.8 FIQ Index Offset Vector Registers (FIQINDEX)
19.9.9 FIQ/IRQ Program Control Registers (FIRQPR[0:3])
19.9.10 Pending Interrupt Read Location Registers (INTREQ[0:3])
19.9.11 Interrupt Enable Set Registers (REQENASET[0:3])
19.9.12 Interrupt Enable Clear Registers (REQENACLR[0:3])
19.9.13 Wake-Up Enable Set Registers (WAKEENASET[0:3])
19.9.14 Wake-Up Enable Clear Registers (WAKEENACLR[0:3])
19.9.15 IRQ Interrupt Vector Register (IRQVECREG)
19.9.16 FIQ Interrupt Vector Register (FIQVECREG)
19.9.17 Capture Event Register (CAPEVT)
19.9.18 VIM Interrupt Control Registers (CHANCTRL[0:31])
20 Direct Memory Access Controller (DMA) Module
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20.1 Overview
20.1.1 Main Features
20.1.2 System Resources Mapping
20.2 Module Operation
20.2.1 Memory Space
20.2.2 DMA Data Access
20.2.3 Addressing Modes
20.2.4 DMA Channel Control Packets
20.2.5 Priority Queue
20.2.6 Data Packing and Unpacking
20.2.7 DMA Request
20.2.8 Auto-Initiation
20.2.9 Interrupts
20.2.10 Debugging
20.2.11 Power Management
20.2.12 FIFO Buffer
20.2.13 Channel Chaining
20.2.14 Request Polarity
20.2.15 Memory Protection
20.2.16 ECC Checking
20.2.17 ECC Testing
20.2.18 Initializing RAM with ECC
20.2.19 Transaction Errors
SPNU563A - March 2018
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Copyright © 2018, Texas Instruments Incorporated
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