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20.3.1.23 Port Assignment Register 2 (PAR2)
31
30
28
Rsvd
CH0PA
R-0
R/WP-0
15
14
12
Rsvd
CH4PA
R-0
R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 20-31. Port Assignment Register 2 (PAR2) Field Descriptions
Bit
Field
Value
31
Reserved
0
30-28
CH16PA
1h
2h
3h
Others
27
Reserved
0
26-24
CH17PA
0-7h
23
Reserved
0
22-20
CH18PA
0-7h
19
Reserved
0
18-16
CH19PA
0-7h
15
Reserved
0
14-12
CH20PA
0-7h
11
Reserved
0
10-8
CH21PA
0-7h
7
Reserved
0
6-4
CH22PA
0-7h
3
Reserved
0
2-0
CH23PA
0-7h
SPNU563A – March 2018
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Figure 20-41. Port Assignment Register 2 (PAR2) [offset = 9Ch]
27
26
Rsvd
CH1PA
R-0
R/WP-0
11
10
Rsvd
CH5PA
R-0
R/WP-0
Description
Reads return 0. Writes have no effect.
These bit fields determine to which port(s) channel 16 is assigned.
Port A and B combined, A read/B write
Port A only
Port B only
Port A and B combined, B read/A write
Reads return 0. Writes have no effect.
These bit fields determine to which port channel 17 is assigned. Refer to CH16PA for bit value
descriptions.
Reads return 0. Writes have no effect.
These bit fields determine to which port channel 18 is assigned. Refer to CH16PA for bit value
descriptions.
Reads return 0. Writes have no effect.
These bit fields determine to which port channel 19 is assigned. Refer to CH16PA for bit value
descriptions.
Reads return 0. Writes have no effect.
These bit fields determine to which port channel 20 is assigned. Refer to CH16PA for bit value
descriptions.
Reads return 0. Writes have no effect.
These bit fields determine to which port channel 21 is assigned. Refer to CH16PA for bit value
descriptions.
Reads return 0. Writes have no effect.
These bit fields determine to which port channel 22 is assigned. Refer to CH16PA for bit value
descriptions.
Reads return 0. Writes have no effect.
These bit fields determine to which port channel 23 is assigned. Refer to CH16PA for bit value
descriptions.
Copyright © 2018, Texas Instruments Incorporated
24
23
22
Rsvd
CH2PA
R-0
R/WP-0
8
7
6
Rsvd
CH6PA
R-0
R/WP-0
Direct Memory Access Controller (DMA) Module
Control Registers and Control Packets
20
19
18
Rsvd
CH3PA
R-0
R/WP-0
4
3
2
Rsvd
CH7PA
R-0
R/WP-0
16
0
741
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