VIM Control Registers
19.9.9 FIQ/IRQ Program Control Registers (FIRQPR[0:3])
The FIQ/IRQ program control registers determine whether a given interrupt request will be either FIQ or
IRQ.
Figure
19-19,
NOTE: Channel 0 and 1 are FIQ only, not impacted by this register.
Figure 19-19. FIQ/IRQ Program Control Register 0 (FIRQPR0) [offset = 10h]
31
15
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Figure 19-20. FIQ/IRQ Program Control Register 1 (FIRQPR1) [offset = F14h]
31
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Figure 19-21. FIQ/IRQ Program Control Register 2 (FIRQPR2) [offset = 18h]
31
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Figure 19-22. FIQ/IRQ Program Control Register 3 (FIRQPR3) [offset = 1Ch]
31
LEGEND: R/W = Read/Write; WP = Write in privilege mode only; -n = value after reset
Table 19-14. FIQ/IRQ Program Control Registers (FIRQPR) Field Descriptions
Bit
Field
127-2
FIRQPRx[n]
1-0
Reserved
686
Vectored Interrupt Manager (VIM) Module
Figure
19-20,
Figure
19-21,
FIRQPR0[31:16]
FIRQPR0[15:2]
R/WP-0
FIRQPR1[63:32]
FIRQPR2[95:64]
FIRQPR3[127:96]
Value
Description
FIQ/IRQ program control bits. These bits determine whether an interrupt request from a peripheral
is of type FIQ or IRQ. Bit FIRQPRx[127:2] corresponds to request channel[127:2].
0
Interrupt request is of IRQ type.
1
Interrupt request is of FIQ type.
3h
Read only. Writes have no effect.
Copyright © 2018, Texas Instruments Incorporated
Figure 19-22
and
Table 19-14
R/WP-0
R/WP-0
R/WP-0
R/WP-0
www.ti.com
describe these registers.
16
2
1
0
Reserved
R-3h
SPNU563A – March 2018
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