Texas Instruments TMS570LC4357 Technical Reference Manual page 169

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2.5.1.18 RTI Clock Source Register (RCLKSRC)
The RCLKSRC register, shown in
Interrupt) clock source selection.
NOTE: Important constraint when the RTI clock source is not VCLK
If the RTIx clock source is chosen to be anything other than the default VCLK, then the RTI
clock needs to be at least three times slower than the VCLK. This can be achieved by
configuring the RTIxCLK divider in this register. This divider is internally bypassed when the
RTIx clock source is VCLK.
31
15
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-37. RTI Clock Source Register (RCLKSRC) Field Descriptions
Bit Field Value
31-10 Reserved
9-8 RTI1DIV
7-4 Reserved
3-0 RTI1SRC
8h-Fh
NOTE: A list of the available clock sources is shown in the
SPNU563A – March 2018
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Figure 2-25
Figure 2-25. RTI Clock Source Register (RCLKSRC) (offset = 50h)
10 9
RTI1DIV
R/WP-1h
Description
0 Reads return 0. Writes have no effect.
RTI clock1 Divider.
0 RTICLK1 divider value is 1.
1h RTICLK1 divider value is 2.
2h RTICLK1 divider value is 4.
3h RTICLK1 divider value is 8.
0 Reads return 0. Writes have no effect.
RTI clock1 source.
0 Clock source0 is the source for RTICLK1.
1h Clock source1 is the source for RTICLK1.
2h Clock source2 is the source for RTICLK1.
3h Clock source3 is the source for RTICLK1.
4h Clock source4 is the source for RTICLK1.
5h Clock source5 is the source for RTICLK1.
6h Clock source6 is the source for RTICLK1.
7h Clock source7 is the source for RTICLK1.
VCLK is the source for RTICLK1.
Copyright © 2018, Texas Instruments Incorporated
System and Peripheral Control Registers
and described in Table 2-37, controls the RTI (Real Time
Reserved
R-0
8 7
Reserved
R-0
Table 2-29.
4 3
RTI1SRC
R/WP-9h
Architecture
16
0
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