Texas Instruments TMS570LC4357 Technical Reference Manual page 165

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2.5.1.15 Clock Domain Disable Clear Register (CDDISCLR)
The CDDISCLR register, shown in
enabled state.
Figure 2-22. Clock Domain Disable Clear Register (CDDISCLR) (offset = 44h)
31
15
Reserved
7 6
Reserved CLRRTICLK1
OFF
R/WP-0 R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 2-34. Clock Domain Disable Clear Register (CDDISCLR) Field Descriptions
Bit Field
31-12 Reserved
11 CLRVCLKA4OFF
10-9 Reserved
8 CLRVCLK3OFF
7 Reserved
6 CLRRTICLK1OFF
5-4 CLRVCLKA[2-1]OFF
3 CLRVCLK2OFF
SPNU563A – March 2018
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Figure 2-22
12
R-0
5 4
CLRVCLKA2 CLRVCLKA1
OFF OFF
R/WP-0 R/WP-0
Value Description
0 Reads return 0. Writes have no effect.
Clear VCLKA4 domain.
0 Read: The VCLKA4 domain is enabled.
Write: The VCLKA4 domain is unchanged.
1 Read: The VCLKA4 domain is disabled.
Write: The VCLKA4 domain is cleared to the enabled state.
0 Reads return zero or one and privilege mode writes allowed.
Clear VCLK3 domain.
0 Read: The VCLK3 domain is enabled.
Write: The VCLK3 domain is unchanged.
1 Read: The VCLK3 domain is disabled.
Write: The VCLK3 domain is cleared to the enabled state.
0-1 Reads return 0 or 1 and privilege mode writes allowed.
Clear RTICLK1 domain.
0 Read: The RTICLK1 domain is enabled.
Write: The RTICLK1 domain is unchanged.
1 Read: The RTICLK1 domain is disabled.
Write: The RTICLK1 domain is cleared to the enabled state.
Clear VCLKA[2-1] domain.
0 Read: The VCLKA[2-1] domain is enabled.
Write: The VCLKA[2-1] domain is unchanged.
1 Read: The VCLKA[2-1] domain is disabled.
Write: The VCLKA[2-1] domain is cleared to the enabled state.
Clear VCLK2 domain.
0 Read: The VCLK2 domain is enabled.
Write: The VCLK2 domain is unchanged.
1 Read: The VCLK2 domain is disabled.
Write: The VCLK2 domain is cleared to the enabled state.
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System and Peripheral Control Registers
and described in Table 2-34, clears clock domains to the
Reserved
R-0
11 10
CLRVCLKA4 Reserved
OFF
R/WP-0 R/WP-0
3 2
CLRVCLK2 CLRVCLKP
OFF OFF
R/WP-0 R/WP-0
16
9 8
Reserved CLRVCLK3
OFF
R/WP-0 R/WP-0
1 0
CLRHCLK CLRGCLK1
OFF OFF
R/WP-0 R/WP-0
165
Architecture