On-Chip Sram - Texas Instruments TMS570LC4357 Technical Reference Manual

Memory Organization

2.2.4 On-Chip SRAM

Several SRAM modules are implemented on the device to support the functionality of the modules
included.
Reads from both the level 1 and level 2 SRAM are protected by ECC calculated inside the CPU. Reads
from all other memories are protected by either the parity with configurable odd or even parity scheme or
ECC that is evaluated in parallel with the actual read.
The TMS570LC43x microcontrollers are targeted towards safety-critical applications, and it is critical for
any failures in the on-chip SRAM modules to be identified before these modules are used for safety-critical
functions. These microcontrollers support a Programmable Built-In Self-Test (PBIST) mechanism that is
used to test each on-chip SRAM module for faults. The PBIST is usually run on device start-up as it is a
destructive test and all contents of the tested SRAM module are overwritten during the test.
The microcontrollers also support a hardware-based auto-initialization of on-chip SRAM modules. This
process also takes into account the read protection scheme implemented for each SRAM module – ECC
or parity.
TI recommends that the PBIST routines be executed on the SRAM modules prior to the auto-initialization.
The following sections describe these two processes.
2.2.4.1 PBIST RAM Grouping and Algorithm Mapping For On-Chip SRAM Modules
Table 2-5 shows the groupings of the various on-chip memories for PBIST. It also lists the memory types
and their assigned RAM Group Select (RGS) and Return Data Select (RDS). Refer to the PBIST chapter
for more details on the usage of the RGS and RDS information.
Module
PBIST_ROM
STC1_1_ROM_R5
STC1_2_ROM_R5
STC2_ROM_N2HET
AWM1
DCAN1
DCAN2
DMA
HTU1
MIBSPI1
MIBSPI2
MIBSPI3
N2HET1
VIM
Reserved
RTP
ATB
AWM2
DCAN3
DCAN4
HTU2
MIBSPI4
MIBSPI5
N2HET2
FTU
FRAY_INBUF_OUTBUF
134
Architecture
Table 2-5. PBIST Memory Grouping
RAM Group #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Copyright © 2018, Texas Instruments Incorporated
RGS RDS
1 1
14 1
14 2
15 1
2 1
3 1 to 6
4 1 to 6
5 1 to 6
6 1 to 6
8 1 to 4
9 1 to 4
10 1 to 4
11 1 to 12
12 1, 2
13 1, 2
16 1 to 12
17 1 to 16
18 1
19 1 to 6
20 1 to 6
21 1 to 6
22 1 to 4
23 1 to 4
24 1 to 12
25 1
26 1 to 8
SPNU563A – March 2018
Submit Documentation Feedback
www.ti.com
Memory Type
ROM
ROM
ROM
ROM
Two-port
Two-port
Two-port
Two-port
Two-port
Two-port
Two-port
Two-port
Two-port
Two-port
Two-port
Two-port
Two-port
Two-port
Two-port
Two-port
Two-port
Two-port
Two-port
Two-port
Two-port
Two-port