Texas Instruments TMS570LC4357 Technical Reference Manual page 174

System and Peripheral Control Registers
2.5.1.23 MSTC Global Status Register (MSTCGSTAT)
The MSTCGSTAT register, shown in
memory hardware initialization and the memory self-test.
Figure 2-30. MSTC Global Status Register (MSTCGSTAT) (offset = 68h)
31
15
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; WP = Write in privileged mode only; -n = value after reset
Table 2-42. MSTC Global Status Register (MSTCGSTAT) Field Descriptions
Bit Field Value
31-9 Reserved 0
8 MINIDONE
0
1
7-1 Reserved 0
0 MSTDONE
0
1
174
Architecture
Figure 2-30
Reserved
9 8
MINIDONE
R/WPC-0
Description
Reads return 0. Writes have no effect.
Memory hardware initialization complete status.
Note: Disabling the MINITGENA key (By writing from a Ah to any other value) will clear the
MINIDONE status bit to 0.
Note: Individual memory initialization status is shown in the MINISTAT register.
Read: Memory hardware initialization is not complete for all memory.
Write: A write of 0 has no effect.
Read: Hardware initialization of all memory is completed.
Write: The bit is cleared to 0.
Reads return 0. Writes have no effect.
Memory self-test run complete status.
Note: Disabling the MSTGENA key (by writing from a Ah to any other value) will clear the
MSTDONE status bit to 0.
Read: Memory self-test is not completed.
Write: A write of 0 has no effect.
Read: Memory self-test is completed.
Write: The bit is cleared to 0.
Copyright © 2018, Texas Instruments Incorporated
and described in Table 2-42, shows the status of the
R-0
7
Reserved
R-0
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16
1 0
MSTDONE
R/WP-0
SPNU563A – March 2018
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