Texas Instruments TMS570LC4357 Technical Reference Manual page 560

Overview
Error Group
1
2
3
Figure 16-2 and Figure 16-3
with register configuration. The total active time of the ERROR pin is controlled by the Low-Time Counter
Preload register (LTCP) and the key register (ESMEPSR) as shown in
details.
error_group1
error_group2
Memory mapped register interface
Peripheral clock (VCLK)
CPU clock (GCLK)
error_group1
error_group2
error_group3
560
Error Signaling Module (ESM)
Table 16-1. ESM Interrupt and ERROR Pin Behavior
Interrupt Generated
configurable interrupt
interrupt generated
no interrupt
show the interrupt response handling and ERROR pin response handling
Figure 16-2. Interrupt Response Handling
Interrupt Enable
Controlled by:
Interrupt Priority
ESMIESR1
Controlled by:
ESMIECR1
ESMILSR1
ESMIESR4
ESMILCR1
ESMIECR4
ESMILSR4
ESMIESR7
ESMILCR4
ESMIECR7
ESMILSR7
ESMILCR7
Figure 16-3. ERROR Pin Response Handling
ERROR Pin Enable
Controlled by:
ESMIEPSR1
ESMIEPCR1
ESMIEPSR4
ESMIEPCR4
ESMIEPSR7
ESMIEPCR7
Copyright © 2018, Texas Instruments Incorporated
Interrupt Priority
configurable priority
high priority
NA
Figure
Low-Priority
Interrupt Handling
High-Priority
Interrupt Handling
Low-Time
Counter Preload
Error Signal
Control
Low-Time
Counter
ESMEPSR
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ERROR Pin Response Generated
configurable output generation
output generated
output generated
16-3. See Section 16.2.2
Low-Priority Interrupt
High-Priority Interrupt
(LTCP )
Device
Output
ERROR
(LTC)
PIN
SPNU563A – March 2018
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