Texas Instruments TMS570LC4357 Technical Reference Manual page 844

Example Configuration
31
15 13 12
000
Reserved
21.4.2.1.5 SDRAM Configuration Register (SDCR) Settings for the EMIF to K4S641632H-TC(L)70
Interface
Finally, the fields of the SDRAM configuration register (SDCR) should be programmed as described in
Table 21-37 to properly interface with the K4S641632H-TC(L)70 device. Based on these settings, a value
of 4720h should be written to SDCR.
now ready to perform read and write accesses to the SDRAM.
Table 21-41. SDCR Field Values For the EMIF to K4S641632H-TC(L)70 Interface
Field Value
SR 0
NM 1
CL 011b
BIT11_9LOCK 1
IBANK 010b
PAGESIZE 0
31 30
0 0
SR Reserved
23
15 14
0 1
Reserved NM
7 6
0
Reserved
844
External Memory Interface (EMIF)
Figure 21-30. SDRAM Refresh Control Register (SDRCR)
0 0000 0000 0000
Reserved
Figure 21-31
Purpose
To avoid placing the EMIF into the self refresh state
To configure the EMIF for a 16-bit data bus
To select a CAS latency of 3
To allow the CL field to be written
To select 4 internal SDRAM banks
To select a page size of 256 words
Figure 21-31. SDRAM Configuration Register (SDCR)
29 28
0
Reserved
00 0000
Reserved
13 12
0 0
Reserved Reserved
4
010
IBANK
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0 0110 0001 1010 (61Ah)
RR
shows how SDCR should be programmed. The EMIF is
0 0000
Reserved
18
11
011
CL
3 2
0
Reserved
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19 18 16
000
Reserved
0
24
17 16
0 0
Reserved Reserved
9 8
1
BIT11_9LOCK
0
000
PAGESIZE
SPNU563A – March 2018
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