Stc1 Segment 0 (Cpu) Test Coverage And Duration - Texas Instruments TMS570LC4357 Technical Reference Manual

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10.5 STC1 Segment 0 (CPU) Test Coverage and Duration

The test coverage and number of test execution cycles (STCCLK) for each test interval are shown in
Table 10-2.
Intervals
SPNU563A – March 2018
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Table 10-2. STC1 Segment 0 Test Coverage and Duration
Test Coverage (%)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
Copyright © 2018, Texas Instruments Incorporated
STC1 Segment 0 (CPU) Test Coverage and Duration
Test Time (Cycles)
0
56.85
64.19
68.76
71.99
75.00
76.61
78.08
79.20
80.18
81.03
81.90
82.58
83.24
83.73
84.15
84.52
84.90
85.26
85.68
86.05
86.40
86.68
86.94
87.21
87.48
87.74
87.98
88.18
88.38
88.56
88.75
88.93
89.10
89.23
89.41
89.55
89.70
89.83
89.96
90.10
90.23
90.33
90.43
Self-Test Controller (STC) Module
0
1629
3258
4887
6516
8145
9774
11403
13032
14661
16290
17919
19548
21177
22806
24435
26064
27693
29322
30951
32580
34209
35838
37467
39096
40725
42354
43983
45612
47241
48870
50499
52128
53757
55386
57015
58644
60273
61902
63531
65160
66789
68418
70047
441