Texas Instruments TMS570LC4357 Technical Reference Manual page 899

www.ti.com
22.3.11 ADC Event Interrupt Enable Control Register (ADEVINTENA)
ADC Event Group Interrupt Enable Control Register (ADEVINTENA) is shown in
described in Table
Figure 22-33. ADC Event Group Interrupt Enable Control Register (ADEVINTENA) [offset = 28h]
31
7
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-17. ADC Event Group Interrupt Enable Control Register (ADEVINTENA) Field Descriptions
Bit Field
31-4 Reserved
3 EV_END_INT_EN
2 Reserved
1 EV_OVR_INT_EN
0 EV_THR_INT_EN
SPNU563A – March 2018
Submit Documentation Feedback
22-17.
4
R-0
Value Description
0 Reads return 0. Writes have no effect.
Event Group Conversion End Interrupt Enable. Refer to
conversion end interrupts.
Any operation mode read/write:
0 No interrupt is generated when conversion of all the channels selected for conversion in the
Event Group is done.
1 An Event Group conversion end interrupt is generated when conversion of all the channels
selected for conversion in the Event Group is done.
0 Reads return 0. Writes have no effect.
Event Group Memory Overrun Interrupt Enable. A memory overrun occurs when the ADC tries
to write a new conversion result to the Event Group results memory which is already full. For
more details on the overrun interrupts, refer to
Any operation mode read/write:
0 No interrupt is generated if an Event Group memory overrun occurs.
1 An Event Group memory overrun interrupt is generated if an Event Group memory overrun
condition occurs.
Event Group Threshold Interrupt Enable. An Event Group threshold interrupt occurs when the
programmed Event Group threshold counter counts down to 0. Refer to
more details.
Any operation mode read/write:
0 No interrupt is generated if the Event Group threshold counter reaches 0.
1 An Event Group threshold interrupt is generated if the Event Group threshold counter reaches
0.
Copyright © 2018, Texas Instruments Incorporated
Reserved
R-0
3 2
EV_END_ Reserved
INT_EN
R/W-0 R-0
Section
Analog To Digital Converter (ADC) Module
ADC Registers
Figure 22-33 and
1
EV_OVR_ EV_THR_
INT_EN INT_EN
R/W-0 R/W-0
Section 22.2.3.1 for more details on the
22.2.3.3.
Section 22.2.3.2
8
0
for
899