Texas Instruments TMS570LC4357 Technical Reference Manual page 49

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22-100. ADC Event Group Channel Selection Mode Control Register (ADEVCHNSELMODECTRL) (offset =
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190h)
22-101. ADC Group1 Channel Selection Mode Control Register (ADG1CHNSELMODECTRL) (offset = 194h)
22-102. ADC Group2 Channel Selection Mode Control Register (ADG1CHNSELMODECTRL) (offset = 198h)
22-103. ADC Event Group Current Count Register (ADEVCURRCOUNT) (offset = 19Ch)
22-104. ADC Event Group Maximum Count Register (ADEVMAXCOUNT) (offset = 1A0h)
22-105. ADC Group1 Current Count Register (ADG1CURRCOUNT) (offset = 1A4h)
22-106. ADC Group1 Maximum Count Register (ADG1MAXCOUNT) (offset = 1A8h)
22-107. ADC Group2 Current Count Register (ADG2CURRCOUNT) (offset = 1ACh)
22-108. ADC Group2 Maximum Count Register (ADG2MAXCOUNT) (offset = 1B0h)
23-1. N2HET Block Diagram
23-2. Specialized Timer Micromachine
23-3. Program Flow Timings
23-4. Use of the Overflow Interrupt Flag (HETEXC2)
23-5. Multi-Resolution Operation Flow Example
23-6. Debug Control Configuration
23-7. Prescaler Configuration
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23-8. I/O Control
23-9. N2HET Loop Resolution Structure for Each Bit
23-10. Loop Resolution Instruction Execution Example
23-11. HR I/O Architecture
23-12. Example of HR Structure Sharing for N2HET Pins 0/1
23-13. XOR-shared HR I/O
23-14. Symmetrical PWM with XOR-sharing Output
23-15. AND-shared HR I/O
23-16. HR0 to HR1 Digital Loopback Logic: LBTYPE[0] = 0
23-17. HR0 to HR1 Analog Loop Back Logic: LBTYPE[0] = 1
23-18. N2HET Input Edge Detection
23-19. ECMP Execution Timings
23-20. High/Low Resolution Modes for ECMP and PWCNT
23-21. PCNT Instruction Timing (With Capture Edge After HR Counter Overflow)
23-22. PCNT Instruction Timing (With Capture Edge Before HR Counter Overflow)
23-23. WCAP Instruction Timing
23-24. I/O Block Diagram Including Pull Control Logic
23-25. N2HET Pin Disable Feature Diagram
23-26. Suppression Filter Counter Operation
23-27. Interrupt Functionality on Instruction Level
23-28. Interrupt Flag/Priority Level Architecture
23-29. Request Line Assignment Example
23-30. Operation of N2HET Count Instructions
23-31. SCNT Count Operation
23-32. ACNT Period Variation Compensations
23-33. N2HET Timings Associated with the Gap Flag (ACNT Deceleration)
23-34. N2HET Timings Associated with the Gap Flag (ACNT Acceleration)
23-35. Angle Generator Principle
23-36. Hardware Angle Generator Block Diagram
23-37. Angle Tick Generation Principle
23-38. New Angle Tick Generation Architecture
23-39. Angle Generation Using Time Based Algorithm
SPNU563A – March 2018
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Copyright © 2018, Texas Instruments Incorporated
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