Texas Instruments TMS570LC4357 Technical Reference Manual page 166

System and Peripheral Control Registers
Table 2-34. Clock Domain Disable Clear Register (CDDISCLR) Field Descriptions (continued)
Bit Field
2 CLRVCLKPOFF
1 CLRHCLKOFF
0 CLRGCLK1OFF
166
Architecture
Value Description
Clear VCLK_periph domain.
0 Read: The VCLK_periph domain is enabled.
Write: The VCLK_periph domain is unchanged.
1 Read: The VCLK_periph domain is disabled.
Write: The VCLK_periph domain is cleared to the enabled state.
Clear HCLK and VCLK_sys domains.
0 Read: The HCLK and VCLK_sys domain is enabled.
Write: The HCLK and VCLK_sys domain is unchanged.
1 Read: The HCLK and VCLK_sys domain is disabled.
Write: The HCLK and VCLK_sys domain is cleared to the enabled state.
Clear GCLK1 domain.
0 Read: The GCLK1 domain is enabled.
Write: The GCLK1 domain is unchanged.
1 Read: The GCLK1 domain is disabled.
Write: The GCLK1 domain is cleared to the enabled state.
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SPNU563A – March 2018
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