Power Domain Clock Disable Register (Pdclkdisreg) - Texas Instruments TMS570LC4357 Technical Reference Manual

PMM Registers

5.4.3 Power Domain Clock Disable Register (PDCLKDISREG)

The default values of the control fields are determined by the device reset configuration word stored in the
TI-OTP region of flash bank 0.
Figure 5-5. Power Domain Clock Disable Register (PDCLKDISREG) (offset = 20h)
31
7
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 5-4. Power Domain Clock Disable Register (PDCLKDISREG) Field Descriptions
Bit Field Value
31-5 Reserved 0
4 PDCLK_DIS[4]
0
1
3 PDCLK_DIS[3]
0
1
2 PDCLK_DIS[2]
0
1
1 PDCLK_DIS[1]
0
1
0 PDCLK_DIS[0]
0
1
288
Power Management Module (PMM)
Reserved
R-0
5 4
PDCLK_DIS[4]
R/WP-n
Description
Reads return 0. Writes have no effect.
Read in User and Privileged Mode returns the current value of PDCLK_DIS[4]. Write in Privileged
Mode only.
Enable clocks to logic power domain PD6.
Disable clocks to logic power domain PD6.
Read in User and Privileged Mode returns the current value of PDCLK_DIS[3]. Write in Privileged
Mode only.
Enable clocks to logic power domain PD5.
Disable clocks to logic power domain PD5.
Read in User and Privileged Mode returns the current value of PDCLK_DIS[2]. Write in Privileged
Mode only
Enable clocks to logic power domain PD4.
Disable clocks to logic power domain PD4.
Read in User and Privileged Mode returns the current value of PDCLK_DIS[1]. Write in Privileged
Mode only.
Enable clocks to logic power domain PD3.
Disable clocks to logic power domain PD3.
Read in User and Privileged Mode returns the current value of PDCLK_DIS[0]. Write in Privileged
Mode only.
Enable clocks to logic power domain PD2.
Disable clocks to logic power domain PD2.
Copyright © 2018, Texas Instruments Incorporated
3 2
PDCLK_DIS[3] PDCLK_DIS[2]
R/WP-n R/WP-n
www.ti.com
8
1 0
PDCLK_DIS[1] PDCLK_DIS[0]
R/WP-n R/WP-n
SPNU563A – March 2018
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