Intel Quark SoC X1000 Design Manual page 9

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Contents-Intel
Quark™ SoC X1000
Figures
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1
Intel
Quark™ SoC X1000 Block Diagram ................................................................... 16
2
Single-Ended Microstrip Diagram................................................................................ 18
3
Differential-Microstrip Diagram .................................................................................. 18
4
Backward Coupling Coefficient ................................................................................... 21
5
Forward Coupling Coefficient ..................................................................................... 21
6
Single-ended Kb Diagram.......................................................................................... 22
7
Differential Kb Diagram............................................................................................. 22
8
Common Glass Cloths Used in PCB Manufacture ........................................................... 24
9
Inhomogeneous Nature of a PCB as Shown in this Cross-Section .................................... 24
10
Effect of Skew on Differential and Common Mode Signals .............................................. 25
11
Cross-Section of PCB Indicating Effect of PCB Fiber Weave ............................................ 25
12
An Example of Offset Routing .................................................................................... 26
13
An Example of Zig-Zag Routing.................................................................................. 27
14
An Example of Slanted Routing .................................................................................. 27
15
Weave Pattern ......................................................................................................... 28
16
DQ/DM - Data Routing Topology for a Single Rank 4L Fly-by Design - PCB Type 3............. 31
17
DQS - Data Strobes Routing Topology for a Single Rank 4L Fly-by Design - PCB Type 3 ..... 31
18
19
MA/BS/CAS/RAS/ WE - Command Routing Topology for a Single Rank 4L Fly-by
Design-PCB Type 3 ................................................................................................. 34
20
Clock Routing Topology for a Single Rank 4L Fly-by Design-PCB Type 3 ......................... 35
21
DDR3 Memory Down Block Diagram ........................................................................... 37
22
Polarity Inversion on a TX to RX Interconnect .............................................................. 42
23
PCI Express* Expansion Card Connector Topology ........................................................ 44
24
USB Port Mapping .................................................................................................... 47
25
Sample Over Current Protection Circuit ....................................................................... 49
26
USB 2.0 MicroUSB Topology ...................................................................................... 49
27
USB 2.0 Mini PCIe Topology ...................................................................................... 51
28
Example of Internal Connector Pin Assignment and Description ..................................... 52
29
Daughter Card......................................................................................................... 53
30
Example of Devices on I2C* Bus ................................................................................ 57
31
SDIO Topology with Connector .................................................................................. 60
32
UART Topology ........................................................................................................ 64
33
SPI0 Topology ......................................................................................................... 68
34
SPI1 Topology ......................................................................................................... 69
35
Clock Integration Distribution Diagram........................................................................ 73
36
Differential Clock Topology for SoC to Clock Receiver .................................................... 75
37
Single Ended Clock Topology for SoC .......................................................................... 76
38
25 MHz Crystal External Load Capacitor Parameters..................................................... 79
39
Legacy SPI Topology (Single Device) .......................................................................... 82
40
SPI Single Flash Device Routing Guidelines for LSPI0_MOSI, LSPI0_MISO,
LSPI0_CS_N,LSPI0_SCK ........................................................................................... 82
41
RTCX1 and RTCX2 Relationship in SoC ........................................................................ 85
42
Example External Circuitry for the SoC RTC ................................................................. 87
43
A Schottky Diode Circuit to Connect RTC External Battery.............................................. 90
44
RTCRST# External Circuit for the SoC RTC................................................................... 91
45
Example GPIO[7:0] Topology level shifted Guideline ..................................................... 94
46
Generic GPIO[7:0] Topology Guideline ........................................................................ 94
47
Intel® Galileo Platform Power Delivery ....................................................................... 98
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48
Quark™ SoC X1000 Power-up Sequence ............................................................ 99
49
platform_s5_pwrok generation................................................................................. 103
50
Power Sequence Timing .......................................................................................... 104
51
Time Domain Capture of Exerciser Operation ............................................................. 108
June 2014
Order Number: 330258-002US
®
Intel
Quark™ SoC X1000
PDG
9

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