Board Mounting Guidelines; Stencil Design - Intel Quark SoC X1000 Design Manual

Exposed Pad* (e-Pad*) Design and SMT Assembly Guide—Intel
Figure 104. Recommended Thermal Via Patterns
B.3

Board Mounting Guidelines

The following are general recommendations for mounting a QFN-48 device on the PCB.
This should serve as the starting point in assembly process development and it is
recommended that the process should be developed based on past experience in
mounting standard, non-thermally/electrically enhanced packages.
B.4

Stencil Design

Note: For maximum thermal/electrical performance, it is required that the exposed pad/slug
on the package be soldered to the land pattern on the PCB. This can be achieved by
applying solder paste on both the pattern for lead attachment as well as on the land
pattern for the exposed pad. While for standard (non-thermally/ -electrically enhanced)
lead-frame based packages the stencil thickness depends on the lead pitch and
package co-planarity, the package standoff must also be considered for the thermally/
electrically enhanced packages to determine the stencil thickness. In this case, a stencil
foil thickness in the range of 5 - 6 mils (or 0.127—0.152 mm) is recommended; likely
or practically, a choice of either 5 mils or 6 mils. Tolerance wise, it should not be worse
than ±0.5 mil.
Note: Industry specialists typically use ±0.1-mil tolerance on stencil for its feasible precision.
The aperture openings should be the same as the solder mask openings on the land
pattern. Since a large stencil opening may result in poor release, the aperture opening
should be subdivided into an array of smaller openings, similar to the thermal land
pattern shown in Figure 104.
Note: Refer to the specific product datasheet for actual dimensions.
June 2014
Order Number: 330258-002US
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Quark™ SoC X1000
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Intel Quark™ SoC X1000
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