Intel Quark SoC X1000 Design Manual page 7

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Contents-Intel Quark™ SoC X1000
17.4.8 Signal Scrambling ................................................................................ 122
17.4.9 Memory Down ..................................................................................... 123
17.4.9.1 Layer Transition...................................................................... 123
17.4.9.2 Clustered Signal Vias............................................................... 123
17.4.10Cable/Adaptor Shielding ........................................................................ 124
17.5 Design Checklist Items..................................................................................... 125
18.0 Electrostatic Discharge (ESD) ................................................................................ 127
18.1 Electrostatic Discharge (ESD) General Introduction .............................................. 127
18.1.1 Description .......................................................................................... 127
18.1.2 Reference Specifications........................................................................ 128
18.2 ESD Protection................................................................................................ 128
18.2.1 ESD Ground-Fill ................................................................................... 129
18.2.2 Ground-Fill Background ......................................................................... 129
18.2.3 USB ESD Diode Recommendation ........................................................... 130
18.2.4 Series RC Filters................................................................................... 130
18.2.5 Sensitive Nets...................................................................................... 133
18.3 USB ESD Component Selection Guidelines .......................................................... 134
18.3.1 USB 2.0 ESD Protection......................................................................... 134
18.3.2 USB 2.0 ESD Protection Diode Vendors ................................................... 136
18.4 Design Checklist Items..................................................................................... 138
19.0 Platform Debug and Test Hooks............................................................................. 139
19.1 Platform Debug and Test Hooks General Introduction ........................................... 139
19.1.1 Description .......................................................................................... 139
19.2 Platform Debug Port ........................................................................................ 139
19.2.1 Signal Routing Guidelines ...................................................................... 139
19.3 JTAG Boundary Scan........................................................................................ 139
19.3.1 Terminating Unused JTAG Signals........................................................... 139
19.4 Additional Debug Support Guidelines.................................................................. 140
19.4.1 Test Points Requirements ...................................................................... 140
20.0 Design for Testability (DFT)................................................................................... 141
20.1 DFT General Introduction ................................................................................. 141
20.1.1 Description .......................................................................................... 141
20.1.2 Reference Documents ........................................................................... 141
20.2 DFT Configuration, Connectivity, Block Diagram .................................................. 141
21.0 LAN Design Considerations and Guidelines ............................................................ 145
21.1 PHY Overview ................................................................................................. 146
21.1.1 PHY Interconnects ................................................................................ 146
21.1.2 RMII Interface ..................................................................................... 147
21.1.2.1 RMII Interface Signals ............................................................. 147
21.1.2.2 RMII Reference Clock .............................................................. 147
21.1.3 MDIO Interface .................................................................................... 147
21.1.3.1 MDIO Connectivity .................................................................. 147
21.2 Platform LAN Design Guidelines......................................................................... 147
21.2.1 General Design Considerations for PHYs .................................................. 147
21.2.1.1 Clock Source .......................................................................... 148
21.2.1.2 Magnetics Module ................................................................... 148
21.2.1.3 Criteria for Integrated Magnetics Electrical Qualification ............... 148
21.2.2 NVM Configuration for PHY Implementations ............................................ 149
21.2.3 LED Example ....................................................................................... 149
21.2.3.1 RBIAS ................................................................................... 150
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21.3 Intel Quark™ SoC X1000 - MDIO/RMII LOM Design Guidelines............................ 151
21.4 General Layout Guidelines ................................................................................ 152
21.5 Layout Considerations...................................................................................... 152
June 2014
Order Number: 330258-002US
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Intel Quark™ SoC X1000
PDG
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