Intel Quark SoC X1000 Design Manual page 12

Tables
1 Platform Stack-up Parameter Values (Microstrip) ..........................................................18
2 Electrical Limits of LH Material Properties .....................................................................20
3 Breakout Geometries for Various I/O Interfaces ............................................................23
4 Max Root Square Sum (RSS) Length vs. Transfer Speed ................................................25
5 This Guideline Supports the Following Configurations.....................................................29
6 DDR3 Channel Signal Groups .....................................................................................30
7 Memory Channel Signals Groups Routing .....................................................................30
8 DQ/DQS Routing Guidelines and Settings for a Single Rank 4L Fly-by Design-PCB Type 3 .31
9 Control - Routing Guidelines and Settings for a Single Rank 4L Fly-by Design-PCB Type 3.33
10 Command Routing Guidelines and Settings for a Single Rank 4L Fly-by Design-PCB Type
3............................................................................................................................34
11 Clock Routing Guidelines and settings for a Single Rank 4L Fly-by Design-PCB Type 3 ......36
12 Precision Resistor Value for DDR3_xxxPU Compensation Inputs ......................................39
13 PCI Express* Root Ports Speed Support.......................................................................41
14 PCIe* Root Ports 1 and2 Supported Configurations .......................................................41
15 SoC PCI Express* Compensation and Voltage Reference Guidelines .................................43
16 PCI Express* Reference Documents ............................................................................43
17 PCI Express* Signal Groups (Standard Card)................................................................43
18 PCI Express* Card Topologies ....................................................................................43
19 PCI Express* Expansion Card Routing PET to Connector.................................................45
20 PCI Express* Expansion Card Routing PER to Connector ................................................46
21 Signal Groups ..........................................................................................................48
22 USB 2.0 External Routing Guidelines MicroUSB .............................................................50
23 USB 2.0 External Routing Guidelines Mini PCIe* ...........................................................51
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24 I C Signals ..............................................................................................................55
25 I2C* Signal Routing Summary....................................................................................56
26 Bus Capacitance Reference Chart................................................................................58
27 Example Bus Capacitance/Pull-Up Resistor Relationship .................................................58
28 SDIO Signals ...........................................................................................................59
29 SDIO Layout Guideline ..............................................................................................60
30 SOC SDIO Pull Up/Down............................................................................................61
31 UART Signals ...........................................................................................................63
32 UART Routing Guideline.............................................................................................64
33 UART Internal Pull Up/Down.......................................................................................64
34 SPI Signals ..............................................................................................................67
35 SPI0_MOSI, SPI0_SCK ..............................................................................................68
36 SPI0_MISO ..............................................................................................................68
37 SPI1_MOSI, SPI1_SCK ..............................................................................................69
38 SPI1_MISO ..............................................................................................................70
39 SOC SPI Internal Pull Up/ Pull Down............................................................................71
40 Signal Groups ..........................................................................................................74
41 Differential Clock Routing Guidelines ...........................................................................75
42 iClock (Single-ended Clocks) ......................................................................................77
43 SPI Signals ..............................................................................................................81
44 LSPI0_MOSI, LSPI0_MISO, LSPI_SS_B, LSPI0_SCK ......................................................82
45 RTC Signals .............................................................................................................85
46 RTC Routing Guidelines .............................................................................................87
47 RTC External RTCRST# Routing Guidelines...................................................................91
48 Asynchronous Legacy Signal Group .............................................................................93
49 Asynchronous Signal General Routing Guideline ...........................................................93
50 GPIO[7:0]l General Routing Guideline .........................................................................94
51 Recommended Platform Power Delivery .......................................................................97
52 Platform Reset Signals ............................................................................................ 101
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Intel Quark™ SoC X1000
PDG
12
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Intel Quark™ SoC X1000-Contents
Order Number: 330258-002US
June 2014