Intel Quark SoC X1000 Design Manual page 164

5. Using a low-quality magnetics module.
6. Reusing an out-of-date physical layer schematic in a Ethernet silicon design. The
terminations and decoupling can be different from one PHY to another.
7. Incorrect differential trace impedances. It is important to have about a 100-
impedance between the two traces within a differential pair. This becomes even
more important as the differential traces become longer. To calculate differential
impedance, many impedance calculators only multiply the single-ended impedance
by two. This does not take into account edge-to-edge capacitive coupling between
the two traces. When the two traces within a differential pair are kept close to each
other, the edge coupling can lower the effective differential impedance by 5  to
20 . Short traces will have fewer problems if the differential impedance is slightly
off target.
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Intel Quark™ SoC X1000
PDG
164
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Intel Quark™ SoC X1000—LAN Design Considerations and Guidelines
June 2014
Order Number: 330258-002US