Power Delivery; Routing Guidelines - Intel Quark SoC X1000 Design Manual

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LAN Design Considerations and Guidelines—Intel
21.21

Power Delivery

In general planes should be used to deliver 3.3 Vdc and the Core voltage. Not using
planes can cause resistive voltage drop and/or inductive voltage drop (due to transient
or static currents). Some of the symptoms of these voltage drops can include higher
EMI, radiated immunity, radiated emissions, IEEE conformance issues, and register
corruption.
Decoupling capacitors (0.1 uF and smaller) should be placed within 250 mils of the LAN
device. They also should be distributed around the PHY and some should be in close
proximity to the power pins.
The bulk capacitors (1.0 uF or greater) should be placed within 1 inch if using a trace
(50 mils wide or wider) or within 1.5 inches if using a plane.
21.22

Routing Guidelines

Table 71.
MAC0_TXDATA<1:0>; MAC0_TXEN; MAC0_MDC; MAC0_MDIO
PCB Routing Layer(s)
Optional
Transmission Line Segment
Routing Layer (Microstrip /
Stripline / Dual Stripline)
Characteristic Impedance
(Single-ended)
Trace Width (w)
Trace Spacing(S2): Between
RMII Signals
Trace Spacing(S3): Between
RMII and other signals
Trace Segment Length
Note:
* Keep La + Lb as short as possible to give the best margin on the overshoot/undershoot violation.
Table 72.
MAC0_RXDATA<1:0>; MAC0_RXDV
PCB Routing Layer(s)
Optional
Transmission Line Segment
Routing Layer (Microstrip /
Stripline / Dual Stripline)
Characteristic Impedance
(Single-ended)
Trace Width (w)
June 2014
Order Number: 330258-002US
®
Quark™ SoC X1000
Breakout
4 Layer
4 Layer
L
L
a
b
MS
MS
4.2 mil
4.2 mil
4.2 mil
10 mil
4.2 mil
10 mil
0.5" max
0.1" - 0.8"
Breakout
4 Layer
4 Layer
L
L
a
b
MS
MS
4.2 mil
4.2 mil
4 Layer
L
c
MS
50 Ω +/- 10%
4.2 mil
10 mil
10 mil
0.1" - 3.0"
4 Layer
L
c
MS
50 Ω +/- 10%
4.2 mil
®
Intel
Quark™ SoC X1000
4 Layer
L
d
MS
4.2 mil
4.2 mil
4.2 mil
0.5" max
4 Layer
L
d
MS
4.2 mil
PDG
165

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