Mdi Differential-Pair Trace Routing For Lan Design; Signal Trace Geometry; Mdi Routing Summary - Intel Quark SoC X1000 Design Manual

21.7

MDI Differential-Pair Trace Routing for LAN Design

Trace routing considerations are important to minimize the effects of crosstalk and
propagation delays on sections of the board where high-speed signals exist. Signal
traces should be kept as short as possible to decrease interference from other signals,
including those propagated through power and ground planes.
21.8

Signal Trace Geometry

One of the key factors in controlling trace EMI radiation are the trace length and the
ratio of trace-width to trace-height above the reference plane. To minimize trace
inductance, high-speed signals and signal layers that are close to a reference or power
plane should be as short and wide as practical. Ideally, the trace-width to trace-height
above the ground plane ratio is between 1:1 and 3:1. To maintain trace impedance, the
width of the trace should be modified when changing from one board layer to another if
the two layers are not equidistant from the neighboring planes.
Each pair of signals should have a differential impedance of 100  ±15%.
When performing a board layout, the automatic router feature of the CAD tool must not
route the differential pairs without intervention. In most cases, the differential pairs will
require manual routing.
Note: Measuring trace impedance for layout designs targeting 100  often results in lower
actual impedance due to over-etching. Designers should verify actual trace impedance
and adjust the layout accordingly. If the actual impedance is consistently low, a target
of 105  to 110  should compensate for over-etching.
It is necessary to compensate for trace-to-trace edge coupling, which can lower the
differential impedance by up to 10 , when the traces within a pair are closer than 30
mils (edge-to-edge).
Table 68.

MDI Routing Summary

Signal group
Microstrip uncoupled single-ended
impedance specification
Microstrip uncoupled differential
impedance specification
Microstrip nominal trace width
Microstrip nominal trace space
Microstrip trace length
Microstrip pair-to-pair space (edge-to-
edge)
Microstrip bus-to-bus spacing
Notes:
1. Pair-to-pair spacing 3 times the dielectric thickness for a maximum distance of 500 mils from the pin.
2. Board designers should ideally target 100 ±15%. If it's not feasible (due to board stack-up) it is
recommended that board designers use a 95 ±10% target differential impedance for MDI with the
expectation that the center of the impedance is always targeted at 95. The ±10% tolerance is
®
Intel Quark™ SoC X1000
PDG
154
®
Intel Quark™ SoC X1000—LAN Design Considerations and Guidelines
Parameter Main Route Guidelines
MDI_PLUS[0:3]
MDI_MINUS[0:3]
50  ±10%
100  ±15%
Design dependent Design dependent
Design dependent Design dependent
4 in (101.6 mm)
maximum
 7 times the thickness of
the thinnest adjacent
dielectric layer
 7 times the thickness of
the thinnest adjacent
dielectric layer
Breakout
Notes
1
Guidelines
2,3
4
3,5
6,7
Figure 95
June 2014
Order Number: 330258-002US