Intel Quark SoC X1000 Design Manual page 166

Table 72. MAC0_RXDATA<1:0>; MAC0_RXDV
Trace Spacing(S2): Between
RMII Signals
Trace Spacing(S3): Between
RMII and other signals
Trace Segment Length
Note: * Keep Lc + Ld as short as possible to give the best margin on the overshoot/undershoot violation.
Number of vias
Rs
Reference Plane
®
Intel Quark™ SoC X1000
PDG
166
®
Intel Quark™ SoC X1000—LAN Design Considerations and Guidelines
Breakout
4.2 mil
4.2 mil
0.5" max
SoC
Breakout
+
La
TX
-
+
RX
-
CFIOHVTEW NO RCOMP
10 mil 10 mil
10 mil 10 mil
0.1" - 3.0" 0.1" - 0.8"
max 2
33ohm +/- 5%
Solid Ground Reference
Rs
Lb Lc
§ §
Order Number: 330258-002US
4.2 mil
4.2 mil
0.5" max
Ld
June 2014