Additional Debug Support Guidelines; Test Points Requirements; Jtag Pullup / Pulldown Requirements - Intel Quark SoC X1000 Design Manual

Table 62.

JTAG PullUp / PullDown Requirements

Pin
TCK
TDI
TMS
TRST_B
TDO
PREQ_B
PRDY_B
19.4

Additional Debug Support Guidelines

19.4.1

Test Points Requirements

Intel recommends users at least provide through-hole vias in a location that is probe
accessible (avoid location that is blocked by thermal solutions or other mechanical
components) and/or pull-up/pull-down resistors, for all the test points so that Intel
would be able to access them when debug by Intel is required.
These test points are for debug and validation purposes, when adding test points effort
must ensure they are not at the detriment of signal integrity.
®
Intel Quark™ SoC X1000
PDG
140
®
Intel Quark™ SoC X1000—Platform Debug and Test Hooks
Direction
Input Internal 20K Pull Down
Input Internal 20K Pull Up
Input Internal 20K Pull Up
Input Internal 20K Pull Up
Output Internal 1K Pull Up
Input Internal 20K Pull Up
Output None
§ §
PullUp/PullDowns
June 2014
Order Number: 330258-002US