Intel Quark SoC X1000 Design Manual page 5

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Contents-Intel Quark™ SoC X1000
8.1 General Introduction.......................................................................................... 63
8.1.1 Description ............................................................................................ 63
8.2 General Purpose Signal Descriptions .................................................................... 63
8.2.1 Signal Groups ........................................................................................ 63
8.3 UART Topology Guidelines .................................................................................. 63
8.4 Additional Guidelines ......................................................................................... 64
8.5 Terminating Unused UART Signals ....................................................................... 64
9.0 General Purpose SPI Interface Design Guidelines.................................................... 67
9.1 General Introduction.......................................................................................... 67
9.1.1 Description ............................................................................................ 67
9.2 General Purpose Signal Descriptions .................................................................... 67
9.2.1 Signal Groups ........................................................................................ 67
9.3 Topology Guidelines........................................................................................... 68
9.4 Terminating Unused SPI Signals .......................................................................... 71
10.0 Platform Clocks Design Guidelines........................................................................... 73
10.1 Platform Clock General Introduction..................................................................... 73
10.1.1 Description ............................................................................................ 73
10.2 Platform Reference Clock Signal Descriptions ........................................................ 74
10.3 Platform Clocks Topology Guidelines .................................................................... 75
10.3.1 Differential Clock Routing Topology........................................................... 75
10.3.1.1 Differential Routing Considerations.............................................. 76
10.3.1.2 Stitching Via Usage and Placement.............................................. 76
10.3.2 Single Ended Clock Routing Topology ........................................................ 76
10.4 25 MHz Crystal and Associated RC Components..................................................... 77
10.4.1 Crystal External Load Capacitor Requirements............................................ 78
10.4.2 25 MHz Crystal Routing Considerations...................................................... 79
11.0 SPI Flash Design Guidelines .................................................................................... 81
11.1 Serial Peripheral Interface (SPI) General Introduction ............................................ 81
11.1.1 Description ............................................................................................ 81
11.2 Serial Peripheral Interface (SPI) Signal Description ................................................ 81
11.3 Serial Peripheral Interface (SPI) Topology Guidelines ............................................. 82
11.3.1 SPI Single Flash Device Topology Guidelines .............................................. 82
11.3.1.1 SPI Single Flash Device Routing Guideline .................................... 82
11.3.1.2 SPI Single Flash Device Length Matching Requirement ................... 83
11.3.2 Boot BIOS Destination ............................................................................ 83
11.4 Serial Flash Vendors .......................................................................................... 83
12.0 RTC Design Guidelines ............................................................................................. 85
12.1 Real Time Clock General Introduction................................................................... 85
12.1.1 Description ............................................................................................ 85
12.2 Real Time Clock Signal Descriptions ..................................................................... 85
12.2.1 Signal Groups ........................................................................................ 85
12.2.2 State Power Good Indicators.................................................................... 86
12.3 Real Time Clock Topology Guidelines.................................................................... 87
12.3.1 RTC External Example Circuit ................................................................... 87
12.3.2 General RTC Layout Considerations........................................................... 88
12.3.3 External Capacitors ................................................................................ 88
12.4 RTC External Battery Connection ......................................................................... 89
12.4.1 RTC Holdup Calculation ........................................................................... 90
12.5 RTC External RTCRST# Circuit ............................................................................ 91
12.6 RTC-Well Input Strap Requirements..................................................................... 92
13.0 Asynchronous Signals Design Guidelines ................................................................. 93
13.1 Asynchronous Signals General Introduction........................................................... 93
June 2014
Order Number: 330258-002US
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Intel Quark™ SoC X1000
PDG
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