Intel Quark SoC X1000 Design Manual page 10

52 Current Loop Radiation of a Transmission Line............................................................ 109
53 Radiation Cancellation of a Differential Line ................................................................ 110
54 An Example of VR EMI Noise .................................................................................... 111
55 VR Noise Can Result In Both SI and EMI Issues .......................................................... 111
56 Simplified Voltage Regulator Module Circuit and VRM EMI Noise .................................... 111
57 The Vx Ripples with/without Gate Resistors (Left: without gate resistor/ Right: with gate
resistor) ................................................................................................................ 112
58 Emission from a Differential line with Various Skews ................................................... 113
59 Changing Referencing, Lack of Referencing, Void-crossing, and Split-crossing are Not
Recommended ....................................................................................................... 114
60 Signal Traces Should be away from Plane Edges ......................................................... 114
61 Keep-out Zone Determined Around IO and Other Connectors ....................................... 115
62 Simple Capacitor Model and an Example of Capacitor Impedance .................................. 115
63 Stitching Capacitors Could Create Low Impedance Path for Return Currents ................... 116
64 Stitching Capacitors Mitigate EMI (Simulated Results).................................................. 117
65 Stitching Capacitors Should be Close to Traces ........................................................... 118
66 Decoupling Capacitors Locations ............................................................................... 118
67 Decoupling Capacitors with Vias ............................................................................... 119
68 Decoupling Capacitors Around the Edges of Power Plane .............................................. 119
69 USB 2.0 Common Mode Choke ................................................................................. 120
70 Demonstration of Spread Spectrum Clocking (SSC)..................................................... 121
71 Spectral Comparison of a Clock Scrambled vs. Unscrambled......................................... 122
72 Ground Vias Placement ........................................................................................... 123
73 Cable/Adaptor Shielding Impacts EMI Significantly ...................................................... 124
74 IEC 61000-4-2 ESD Waveform ................................................................................. 128
75 Mutual L and C (Lm, Cm) Coupling............................................................................ 129
76 Ground Shape Along the I/O Edge of the Board .......................................................... 130
77 Series RC Filter for ESD Mitigation on Asynchronous Nets............................................. 131
78 Frequency Response of The Series RC Filter ............................................................... 131
79 ESD Noise Suppression Using Series RC Filters ........................................................... 132
80 Signal Integrity Analysis With Series RC Filters ........................................................... 133
81 Circuit Diagram of Direct Injection Method ................................................................. 134
82 USB 2.0 ESD Protection Devices ............................................................................... 135
83 Typical Integrated Diode Array Package..................................................................... 135
84 Layout Example of USB 2.0 with ESD Diode Array ....................................................... 136
85 Differential S-parameters from Ceramic 1-line, Si 4-line and Si 6-line
ESD Protection Devices. .......................................................................................... 137
86 Example of Test Bead on a Stub (Not Preferred) ......................................................... 142
87 Example of Differential Test Bead with Matched Placement........................................... 142
88 Bead Formed Over Solder-Mask Opening ................................................................... 143
89 Bead Placed on Existing Via ..................................................................................... 144
90 SOC/PHY Interface Connections................................................................................ 145
91 LED Hardware Configuration .................................................................................... 150
92 Single PHY Solution Interconnect .............................................................................. 151
93 PLC Placement: At Least One Inch from I/O Backplane ................................................ 153
94 Effect of LAN Device Placed Too Close To a RJ-45 Connector or Chassis Opening ............. 153
95 MDI Trace Geometry............................................................................................... 156
96 MDI Differential Trace Geometry............................................................................... 157
97 Trace Transitioning Layers and Crossing Plane Splits ................................................... 159
98 Via Connecting GND to GND..................................................................................... 160
99 Stitching Capacitor between Vias Connecting GND to GND ........................................... 160
100 Ideal Ground Split Implementation ........................................................................... 161
101 Ground Layout with USB.......................................................................................... 162
102 Typical ePAD* Land Pattern ..................................................................................... 182
103 Typical Thermal Pad and Via Recommendations .......................................................... 182
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Intel Quark™ SoC X1000
PDG
10
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Intel Quark™ SoC X1000-Contents
Order Number: 330258-002US
June 2014