Design For Testability (Dft); Dft General Introduction; Description; Reference Documents - Intel Quark SoC X1000 Design Manual

Design for Testability (DFT)—Intel
20.0

Design for Testability (DFT)

20.1

DFT General Introduction

20.1.1

Description

This section provides guidelines for implementing Design for Testability (DFT) on this
platform for supporting customer to define their DFT into their product in order to
maximize test coverage in manufacturing tests.
All interfaces will support a minimum of one test bead per signal and a maximum of
two test beads per signal. When implementing DFT, it is recommended to use existing
vias, pads or pins wherever possible. If existing vias or pads can not be used, they may
be added but the total number of vias specified for each interface can not be exceeded.
20.1.2

Reference Documents

VREG Controller's data sheet
®
Intel Quark SoC X1000 Datasheet
20.2

DFT Configuration, Connectivity, Block Diagram

DFT probe points can be placed anywhere on the trace. It is preferred to place test
beads directly on the trace or vias. However, if beads can not be placed directly on the
trace, the stub to the bead should be less than 50 mils (1.27 mm), shown in
Test beads for differential signals should be matched on the differential pair within ±5
mils. If required, it is ok to break the differential pair spacing requirements for a short
route in order to place both test beads in a matched location.
Example is shown in
or beginning of a trace in order to avoid signal reflection/refraction.
June 2014
Order Number: 330258-002US
®
Quark™ SoC X1000
Title
Figure 87. Also, it is recommended to place test beads at the end
Location
TBD
https://commu-
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community/makers/
documentation/
quarkdocuments
Figure 86.
®
Intel Quark™ SoC X1000
PDG
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