Electrostatic Discharge (Esd); Electrostatic Discharge (Esd) General Introduction; Description - Intel Quark SoC X1000 Design Manual

Electrostatic Discharge (ESD)—Intel
18.0

Electrostatic Discharge (ESD)

18.1

Electrostatic Discharge (ESD) General Introduction

18.1.1

Description

All electronic equipment that is sold into the European Union and mutually recognized
countries, must possess the CE mark which designates it has passed a required set of
test standards; these test requirements include system testing for ESD protection. The
purpose of the ESD test is to demonstrate that a system can withstand static
discharges encountered in normal handling and system operation. It is important to
emphasize designing for ESD in the early project stages help reduce costly and time
consuming debug and design changes late in the development cycle.
Besides standard regulatory requirements for system-level ESD, an emerging threat to
component reliability and quality has been the direct and indirect discharge of ESD to
the signals and pins of user accessible I/O interfaces; hot-plug. Traditional silicon level
ESD protection, meant to handle JEDEC and ESDA procedures, may not be able to
respond to the 200ps to 1ns high inrush current of an IEC 61000-4-2 ESD type event.
Depending on the ESD characteristics and level encountered, the failure mode of
semiconductors will behave and occur differently. Outside the instantaneous logic error
or catastrophic failure, repetitive ESD stress may produce degradation of failures over
time and is referred to as latent ESD defects. This occurs when an ESD pulse is not
strong enough to destroy a device but alternatively causes undetected degradation.
Although the device may suffer this degradation, it may still function within data sheet
parameters. A device can be subjected to numerous weak ESD pulses, with each one
further degrading a device before it succumbs to a noticeable failure. There is no known
practical methodology able to screen for devices with latent defects.
The IEC 61000-4-2 ESD pulse is a transient with a very fast rising edge. The IEC
61000-4-2 specification defines the time domain waveform of the ESD pulse. The
risetime of the waveform is between 0.7 ns to 1 ns with a specified peak current of
3.75 A/kV. Additional current waveform requirements are 2 A/kV at 30 ns and 1 A/kV at
60 ns.
June 2014
Order Number: 330258-002US
®
Quark™ SoC X1000
®
Intel Quark™ SoC X1000
PDG
127